Quantum Bump Integration Engineer

Job Title

Quantum Bump Integration Engineer

Role Summary

R&D process engineer responsible for developing and integrating cryogenic, superconducting bump interconnects for scalable quantum hardware packaging. The role sits in the Quantum Advanced Packaging team at Fab9 and coordinates wafer-level processing, assembly, qualification, and partner engagements.

Experience Level

Senior-level role. The posting requests a Master’s degree with at least 8 years of related experience; PhD and 5+ years preferred.

Responsibilities

Design, develop, and scale bump/interconnect processes for cryogenic quantum packaging; move technologies from R&D toward pilot and manufacturing while ensuring electrical and mechanical reliability at cryogenic temperatures.

• Lead development of cryogenic-compatible bump technologies (e.g., indium, SnAg, Cu pillar, superconducting metals).
• Define and optimize bump structures, metallurgy, and process flows for superconducting integration.
• Establish process windows for electrical, thermal, and mechanical stability across mK–K temperatures.
• Own end-to-end bump integration from wafer processing to assembly and qualification.
• Develop integration schemes for 2.5D/3D architectures (interposers, TSVs, die-to-wafer flows).
• Coordinate unit processes (plating, litho, CMP, bonding) with system-level packaging requirements.
• Enable rapid prototyping and transfer of development lots; support scale-up to pilot/high-volume manufacturing.
• Identify and analyze failure modes; apply DOE, statistical analysis, and root-cause methods.
• Collaborate with device, cryogenics, packaging, modeling, test, and vendor partners.
• Generate process documentation, specifications, technical reports, and contribute to IP and publications.

Requirements

Key qualifications and skills required to perform the role. Education items are summarized under Education Requirements below.

• In-depth knowledge of BEOL processes and integration, bump/wafer finish integration, wafer test/probe, OSAT collaboration, and package development & assembly.
• Experience with process development for low-temperature/cryogenic interconnects and sensitivity to CTE mismatch, diffusion, and fatigue.
• Strong problem-solving and technical troubleshooting skills, including design of experiments (DOE) and statistical analysis.
• Experience defining process flows, establishing process windows, and transitioning processes to manufacturing.
• Familiarity with electrical and RF/microwave characterization of interconnects at cryogenic temperatures.
• Ability to interface with vendors, tool suppliers, and OSAT partners for development and scale-up.
• English fluency (written and verbal).
• Travel availability up to 10%.

Education Requirements

Master’s degree in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science, or a related field required. The posting specifies an MS with at least 8 years of related experience; a PhD is preferred (with at least 5 years of related experience). Applicants must have at least a 3.0 GPA or equivalent academic standing. "Related field" or equivalent practical experience is acceptable per the listing.

About the Company

Company: GlobalFoundries

Headquarters: Saratoga Springs, New York, USA

GlobalFoundries is a leading contract manufacturer for the global semiconductor industry, with facilities in multiple countries, including the USA. The company develops a broad portfolio of semiconductor technologies and employs around 13,000 people worldwide. GlobalFoundries focuses on enhancing competitiveness in specialized application solutions and fostering innovation in mobile communications, consumer electronics, and automotive applications.