Product Engineering Architect - High-Speed IP PHY

Job Title

Product Engineering Architect - High-Speed IP PHY

Role Summary

Technical lead and product owner for post‑sales support and adoption of high‑performance interface PHY IP. Works with global R&D, validation, applications, and customers to resolve integration and silicon bring‑up issues and to drive product readiness.

Part of a product engineering team supporting high‑speed interfaces (PCIe, UCIe, USB, DPHY, Ethernet, DDR, LPDDR, GDDR, HBM); combines customer engagement, technical leadership, and local team coordination.

Experience Level

Senior. Role expects extensive prior experience in high‑speed interface IP and customer‑facing silicon support (guidance: PhD ~10+ years; MS ~12+ years; BS ~15+ years).

Responsibilities

Lead technical activities across the product lifecycle and serve as the primary engineering contact for customers and internal teams.

• Serve as primary product engineering owner for high‑speed interface IP at the customer level (PCIe, UCIe, Ethernet, USB, DDR, LPDDR, GDDR, HBM).
• Lead customer engagements: technical discussions, design reviews, and deployment strategy.
• Drive resolution of complex subsystem integration, SoC integration reviews, and implementation issues.
• Provide technical leadership for RTL development, gate‑level simulation, and timing closure strategies.
• Define and improve integration methodologies, checklists, and customer collateral.
• Lead post‑silicon bring‑up, debug activities, and customer deployment efforts.
• Coordinate cross‑functional work with R&D, validation, and applications to achieve product readiness.
• Mentor and lead local team members; manage priorities and escalations.
• Maintain status, priorities, and execution tracking for ongoing customer support activities.
• Leverage tools and automation to improve debug efficiency and engineering quality.

Requirements

Must‑have technical skills, customer leadership, and the ability to drive cross‑functional execution. Preferred items are listed separately.

• Must-have: Extensive experience with high‑speed interface IP and subsystem integration.
• Must-have: Deep knowledge of RTL design, gate‑level verification, simulation methodologies, synthesis, STA, and timing closure.
• Must-have: Experience with post‑silicon bring‑up, debug, and delivering customer deployments.
• Must-have: Familiarity with DFT methodologies, test flows, and system validation approaches.
• Must-have: Proven ability to lead cross‑functional technical efforts, manage escalations, and represent the organization in customer‑facing roles.
• Must-have: Strong communication skills and ability to influence customers and internal stakeholders; experience mentoring and coordinating local teams.
• Nice-to-have: Backend flow knowledge, analog/mixed‑signal understanding, or experience with memory and high‑speed communication interfaces (DDR/LPDDR/GDDR, PCIe, UCIe, Ethernet, USB).
• Nice-to-have: Experience in customer silicon debug and bring‑up environments.
• Nice-to-have: Familiarity with AI‑assisted workflows, data‑driven debug techniques, and automation to improve turnaround time.

Education Requirements

Required: Bachelor's in Electrical Engineering, Computer Engineering, or a related field with ~15+ years experience; Master's with ~12+ years; PhD with ~10+ years of relevant experience. Fields referenced include electrical engineering and computer engineering; equivalent industry experience consistent with the stated years is expected.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.