Principal Verification Engineer (Memory Interface Chips)
Join the Memory Interface Chips (MIC) team in Bangalore to lead verification efforts for high-speed DDR products. The role covers full verification lifecycle from understanding design requirements through verification sign-off and supporting post-tapeout validation.
This is a hybrid, full-time role reporting to the Senior Director and collaborating with architects, designers and post-silicon teams to ensure verification closure for complex IP and subsystems.
Senior β requires approximately 10+ years of relevant verification experience.
Primary responsibilities focus on planning, executing and delivering verification sign-off for block/IP/subsystem designs.
Key technical and professional requirements.
Bachelor's or Master's degree in Electronics. The posting also specifies approximately 10+ years of relevant verification experience.
Company: Rambus
Headquarters: Sunnyvale, California, USA
Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.
