Principal Verification Engineer
Principal Verification Engineer on the Memory Interface Chips (MIC) team in Bangalore, responsible for planning and executing verification for high-speed DDR products through sign-off and supporting validation post-tapeout.
The role reports to the Senior Director and works closely with architects, designers and post-silicon teams in a hybrid work model (average three days onsite per week).
Senior β requires extensive verification experience; posting specifies 10+ years of relevant experience.
The main responsibility is to close verification requirements from specification to sign-off for block/IP/sub-system designs.
Must-have technical skills and attributes for successful performance in this role.
Bachelor's or Master's degree in Electronics (specified). The posting specifies 10+ years of relevant experience in addition to the degree requirement.
Company: Rambus
Headquarters: Sunnyvale, California, USA
Rambus is a global leader in advanced semiconductor and technology solutions, specializing in enhancing data access and improving performance in computing, networking, and storage applications. The company is known for its innovative IP and solutions in memory, security, and interface technologies. With a strong focus on research and development, Rambus continues to push the boundaries of technology to meet the growing demands of the digital age.
