Principal Validation Lead

Job Title

Principal Validation Lead

Role Summary

The Principal Validation Lead owns lab validation strategy and execution for advanced ASIC/SoC products that integrate CXL, HBM, DDR, PCIe, and high-speed SerDes. The role combines hands-on silicon bring-up and debug with technical leadership of validation activities and cross-functional coordination.

Experience Level

Senior. Requires substantial industry validation experience and proven technical leadership in silicon or system bring-up and lab validation (typically 5+ years of hands-on validation experience).

Responsibilities

Lead validation planning, execution, and technical direction for complex ASIC/SoC projects.

• Define validation strategy and test plans covering functionality, performance, power, margining, and interoperability for CXL/PCIe/DDR/HBM/SerDes interfaces.
• Lead silicon and platform bring-up (boards, power, clocks, resets) and interface-level validation.
• Provide technical direction and task prioritization for validation engineers; review test plans and debug approaches.
• Configure and operate advanced lab equipment (oscilloscopes, probes, logic analyzers, protocol analyzers, BERTs, pattern generators, power supplies, environmental chambers).
• Develop and maintain lab automation and data analysis infrastructure to improve coverage, throughput, and reproducibility.
• Analyze large data sets to characterize high-speed links and memory interfaces (BER, eye diagrams, jitter, margins, throughput, latency, power).
• Lead root-cause investigations across silicon, firmware, board design, and test setups; coordinate cross-functional issue closure.
• Document validation methodologies, lab setups, and results; report status, risks, and mitigations to project leadership.
• Mentor and coach junior validation engineers and help establish scalable lab validation practices.

Requirements

Key skills and experience required for successful performance in this role.

• Extensive hands-on experience in silicon or system validation, including lab bring-up and debug.
• Strong expertise in at least two of the following: CXL (2.0/3.x), PCIe (Gen4/Gen5/Gen6), DDR (DDR4/DDR5), HBM (HBM2/2E/3), high-speed SerDes.
• Proven track record leading bring-up and validation from first silicon through production.
• Deep practical experience with high-speed measurement techniques and lab equipment.
• Strong scripting and lab automation skills (examples: Python, TCL, shell, MATLAB) for test control and data analysis.
• Ability to drive cross-functional debug, communicate complex technical issues clearly, and close issues with design/DFT/firmware/product teams.
• Nice-to-have: experience leading small validation teams, familiarity with DFT features (scan, BIST, JTAG), and experience with signal integrity / power integrity practices.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field (posted requirement: Bachelor's + ~10–15 years experience) or a Master's degree and/or PhD in Computer Science, Electrical Engineering, or related fields (posted guidance: Master's/PhD + ~5–10 years experience). Preferred: Master's in Electrical Engineering or Computer Engineering. Related technical fields acceptable as stated in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.