Principal Validation Engineer

Job Title

Principal Validation Engineer

Role Summary

Principal-level silicon validation engineer responsible for post-silicon PHY and functional validation of high-bandwidth switch devices. The role works on advanced Si nodes and packaging targeting datacenter switch products and requires close collaboration with design, firmware, and systems teams to verify PHY, PCIe, UALink and Ethernet functionality.

Experience Level

Senior. The posting expects experienced candidates; see Education Requirements for degree-and-experience combinations that the team targets.

Responsibilities

Key day-to-day responsibilities for this role include:

• Own PHY and functional validation for post-silicon devices, including planning, execution, and reporting.
• Define, document and execute comprehensive validation and test plans for switch devices.
• Perform lab-based silicon bring-up and unit testing focused on PCIe physical and PCS layer hardware and firmware; extend testing into protocol-layer validation.
• Perform high-speed signal validation and analysis (eye diagram, jitter, BER) using oscilloscopes, BERTs and network analyzers.
• Analyze and debug PHY and protocol issues across PCIe, UALink and Ethernet stacks.
• Coordinate with design, firmware and system teams to reproduce failures and drive root-cause resolution.
• Maintain validation environments, capture results, and produce technical reports documenting findings and fix verification.

Requirements

Must-have technical skills and qualifications:

• Strong understanding of high-speed SERDES fundamentals and equalization techniques.
• Deep familiarity with PCIe, UALink and Ethernet protocols at physical and protocol layers.
• 5+ years of hands-on experience with high-speed I/O testing, debugging and validation.
• Proven lab skills: system bring-up, system-level testing and hardware/firmware debug.
• Experienced with SERDES characterization equipment (oscilloscope, BERT, network analyzer).
• Strong analytical, problem-solving and communication skills.
• Ability to obtain access to export-controlled technology; candidates may be subject to export-license review.

Preferred (nice-to-have):

• Experience with PCIe interface characterization and validation.
• Experience with Ethernet and/or UALink validation.
• Knowledge of PIPE interface, PCS, MAC and other physical/protocol layer details.
• Ability to read board schematics and PCB layout.
• SERDES modeling experience and working knowledge of Python.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering or a related technical field with 10+ years of related professional experience; OR a Master’s degree or PhD in Computer Science, Electrical Engineering or a related field with 5+ years of related professional experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.