Principal Timing Engineer

Job Title

Principal Timing Engineer

Role Summary

Engineer responsible for post-RTL ASIC design flow for SerDes and mixed-signal IP, focused on synthesis, timing closure, DFT, and ECOs. Embedded in the Central Engineering AMS-IP team that delivers SerDes PHY and other analog/mixed-signal IP across product lines.

The role collaborates with analog and digital design teams and supports product teams through pre- and post-silicon phases to deliver competitive IP solutions.

Experience Level

Senior — typically 10–12+ years of relevant ASIC post-RTL experience (role expects extensive post-RTL and physical timing closure experience).

Responsibilities

Primary responsibilities include:

• Lead post-RTL activities including synthesis, static timing analysis, physical design support, and ECO implementation at block and chip levels.
• Perform logic and physical synthesis and static timing analysis for SerDes IPs across data rates (10Gbps–224Gbps).
• Support DFT generation and verification and integrate DFT into the design flow.
• Develop and improve design methodology, place-and-route practices, and PnR flow for mixed-signal designs.
• Collaborate with analog and digital teams on floorplanning, timing closure, clock-tree and power planning as required.
• Provide pre- and post-silicon support to product teams and respond to design changes and ECOs.

Requirements

Must-have and preferred technical skills:

• Must-have: Extensive post-RTL experience (synthesis, timing analysis, physical design) including custom placement/routing for mixed-signal designs and block/top-level timing closure.
• Proficient with logic or physical synthesis using Synopsys or Cadence tools.
• Static timing analysis experience with PrimeTime.
• Physical design experience at 28nm process nodes and beyond.
• DFT generation and verification experience.
• Strong scripting skills in Perl and Tcl.
• Good communication skills and ability to work effectively in a design team; flexible to support multiple post-RTL activities.
• Nice-to-have: Low-power design, IR-drop analysis, circuit-level or custom design experience, floorplanning, clock-tree synthesis, power planning/analysis, signal integrity, and PnR flow development.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or related field with 12+ years of relevant professional experience; or Master’s degree/PhD in Computer Science, Electrical Engineering, or related field with 10+ years of experience. (Degree and experience expectations are stated in the source.)

Expected Base Pay Range (CAD): 145,800 - 194,400 per annum.

Interviews: use of AI tools during interviews is not permitted; unauthorized use may disqualify a candidate.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.