Principal Test Engineer / DFT Architect

Job Title

Principal Test Engineer / DFT Architect

Role Summary

Lead the definition of testability and production test strategy for advanced semiconductor products from concept through production release. Act as the technical lead on DFT and ATE strategy, bridging design, product engineering, test engineering, validation, quality, and manufacturing.

Primary mission: ensure products are designed for measurable, controllable, and scalable production test, minimize test cost and cycle time, and improve yield learning and production readiness.

Experience Level

Senior-level individual contributor. Typically requires 12+ years of semiconductor experience in test engineering, DFT, product engineering, validation, design, or product industrialization.

Responsibilities

Key responsibilities include defining strategy, influencing design, and enabling scalable production test.

• Define product-level test and DFT strategy: wafer probe, final test, characterization, qualification, GRR, production test flow, and cost-of-test targets.
• Partner with design, systems, validation, product engineering, quality, operations, and manufacturing to define DFT and test requirements early in the lifecycle.
• Drive requirements for test muxes, scan/debug access, analog observability, digital controllability, embedded monitors, BIST, trim/calibration access, fuse/NVM test modes, and diagnostics.
• Review schematics, architecture documents, specs, register maps, and test-mode plans to identify and close testability gaps before design freeze.
• Establish reusable DFT and test-access standards for power, analog, mixed-signal, and digitally assisted products.
• Define ATE platform strategy: tester selection, instrument usage, multisite targets, handler/prober compatibility, hardware reuse, and test-time optimization.
• Establish test flows, binning methodology, screening strategy, guardband approach, and data-collection conventions.
• Assess feasibility and methods for critical tests (high-voltage stress, analog parametric, digital interfaces, trim/calibration, NVM programming, wafer-level characterization).
• Influence test hardware architecture (load boards, probe cards, sockets, interface circuitry) to improve accuracy and multisite scalability.
• Support complex silicon and production debug by correlating ATE data, bench data, circuit behavior, and process/yield trends.
• Lead testability reviews, create architecture documentation, DFT checklists, production-readiness criteria, and mentor engineers on DFT and test methodology.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• 12+ years semiconductor experience in test engineering, DFT, product engineering, validation, design, or product industrialization.
• Hands-on experience with ATE test development and production test strategy, including multisite test and test-time optimization.
• Experience testing analog, mixed-signal, digital, and/or power-management ICs.
• Strong understanding of ATE instrumentation, timing, digital pattern execution, analog measurements, handler/prober interfaces, and test hardware.
• Practical circuit knowledge: references, regulators, ADC/DACs, digital interfaces, clocks, trims, NVM/fuse structures, protection features, and test-access circuitry.
• Familiarity with wafer sort/final test strategy, production test flows, yield learning, quality screening, and test-cost modeling.
• Strong debug skills using ATE results, bench measurements, simulation, failure analysis, and production trends.
• Experience with scripting, automation, and data analysis tools (e.g., Python, JMP, MATLAB, SQL) for test development and analytics.
• Demonstrated ability to lead cross-functional technical reviews and influence without direct authority.
• Nice-to-have: experience with automotive/high-voltage/power-management products, familiarity with specific ATE platforms (Advantest V93K, Teradyne/Microflex, ETS, COHU/DiamondX, SPEA), scan/BIST/memory test methods, trim/calibration and NVM programming, and AI/ML applied to test data.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field is required; an advanced degree is preferred. (The posting lists these degree expectations explicitly.)

About the Company

Company: Renesas

Headquarters: Hitachinaka, Japan

Renesas is a global leader in embedded semiconductor solutions, providing high-quality products across automotive, industrial, infrastructure, and IoT sectors. With over 22,000 employees in more than 30 countries, the company focuses on scalable solutions that enhance user experience and drive innovation while committed to sustainability and energy efficiency.