Principal Test Development Engineer

Job Title

Principal Test Development Engineer

Role Summary

Principal-level test development engineer in Operations responsible for developing and validating production, wafer-sort, and characterization test programs for Marvell silicon. Work closely with design, DFT/DFM, and product engineering to ensure testability, meet product specifications, and optimize test flow and yield.

Base pay range (USD): 136,880 - 205,000 per year. This role may participate in bonus and equity plans.

Experience Level

Senior (Principal). The posting indicates typical education/experience combinations: Bachelor's degree + 5–10 years, or Master's degree + 3–5 years. Significant prior ATE/test development experience is expected.

Responsibilities

Primary responsibilities include development, validation, and optimization of test programs and test hardware for high-speed semiconductor products.

• Develop characterization, production, and wafer-sort test programs on the Advantest 93K ATE platform.
• Design and validate tester hardware for high-speed testing and manage test pattern conversion from design simulation to ATE format.
• Create detailed test plans, methodologies, and documentation to meet product specifications.
• Lead test flow optimization efforts: reduce test time, improve yield, and manage insertion/removal of tests in production releases.
• Participate in testability reviews with DFT/DFM and design teams to define and enhance yield and test strategies.
• Collaborate with product and cross-functional teams to release production test programs and resolve test issues.

Requirements

Must-have technical skills and experience for successful performance in this role.

• Minimum 6+ years test program development experience on the Advantest 93K ATE platform.
• Proven experience in ATE testing, test methodology, silicon process knowledge, and DFT/DFM.
• 4+ years high-speed digital testing experience and hands-on experience with C/C++, Perl, Python, and Linux environments.
• Experience converting test patterns from simulation environment to ATE format and validating tester hardware.
• Strong problem-solving, collaboration, interpersonal, and communication skills; ability to multi-task in a fast-paced environment and demonstrate urgency and accountability.

Nice-to-have:

• Experience designing tester hardware or additional ATE platforms beyond Advantest 93K.
• Prior leadership in test flow optimization, yield improvement projects, or test automation initiatives.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field (posting lists Bachelor's + 5–10 years), or a Master’s degree in Computer Science, Electrical Engineering, or related field (posting lists Master’s + 3–5 years). Specific degree fields: Computer Science and Electrical Engineering. Years-of-experience guidance is included above.

May require eligibility to access export-controlled technology; non-U.S. applicants may be subject to an export license review. Accommodation requests: contact Marvell HR Helpdesk at TAOps@marvell.com.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.