Principal Test Development Engineer

Job Title

Principal Test Development Engineer

Role Summary

Principal-level test development engineer responsible for developing ATE test solutions for characterization, wafer sort and production of Marvell silicon. Work closely with design and DFx teams to ensure testability, produce test plans and test programs, and design ATE hardware when required.

Primary platforms include Advantest 93K and Teradyne tester families; the role focuses on high-speed digital interfaces and production-ready test flows.

Experience Level

Senior / Principal. The posting expects experienced candidates — typically 10+ years of relevant professional experience (or ~5+ years with an advanced degree as detailed below).

Responsibilities

Primary responsibilities include development, validation and release of ATE test solutions and related hardware/software for high-speed silicon products.

• Lead development of ATE test solutions for characterization, wafer sort and production on Advantest 93K and/or Teradyne platforms.
• Design and develop high-speed ATE hardware and fixtures to support test requirements.
• Create detailed test plans, methodologies, and documentation that meet product specifications.
• Convert test patterns from design/simulation environments to ATE formats and integrate into test programs.
• Collaborate with DFx, design, and product teams on testability reviews and yield improvement activities.
• Optimize test flows to reduce test time, remove unnecessary steps, and improve yield.
• Release and maintain production test programs and support product qualification and ramp.

Requirements

Must-have technical skills, platform experience, and professional attributes.

• Proven expertise in test program development on Advantest 93K and/or Teradyne tester platforms.
• Hands-on experience with ATE testing, test methodology, silicon process, DFT/DFM, and high-speed digital testing.
• Proficiency in C/C++, Perl, Python and comfortable in a Linux development environment.
• Experience testing high-speed interfaces, including NRZ and PAM4 signaling.
• Working knowledge of scan and MBIST DFT test methodologies.
• Experience designing complex, high-performance ATE hardware.
• Strong communication, teamwork, problem-solving skills, and ability to work independently in a fast-paced environment.
• Role may require eligibility to access export-controlled technology; applicants may be subject to export license review prior to employment.
• Reasonable accommodation requests during the selection process can be directed to Marvell HR Helpdesk at TAOps@marvell.com.

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or a related field plus 10+ years of related professional experience; or a Master’s degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 5+ years of related experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.