Principal Technical Program Manager — Hardware/Silicon

Job Title

Principal Technical Program Manager — Hardware/Silicon

Role Summary

Drive engineering program management for the global hardware organization, focusing on predictable delivery of chip development programs. Partner with engineering and product leaders to translate company objectives into executable plans, improve planning and execution practices, and align cross-functional teams across geographies.

Experience Level

Senior — 10+ years in chip/IC development; at least 3 years in a technical program manager role.

Responsibilities

Manage end-to-end program delivery across the chip development lifecycle and create scalable processes to improve predictability and quality.

• Lead program management across chip development phases including architecture, RTL design, verification, emulation, power/performance modeling, DFT, STA, physical design, packaging, analog/system design and tapeout.
• Establish predictable milestones and delivery plans for internal teams and 3rd-party partners (IPs, VIPs, physical design).
• Coordinate schedules and deliveries across teams in North America and India.
• Define metrics, build dashboards, and report program health to stakeholders.
• Create playbooks and best practices for program management and cross-functional deliveries.
• Identify, track, and mitigate risks to schedule and quality.
• Act as the liaison between hardware teams and company leadership with clear, concise status and trade-off recommendations.
• Manage dependencies with Product, Hardware, and external partners to align on commitments and timelines.

Requirements

Must-have technical program management experience in chip/IC development and demonstrated ability to scale processes in a fast-moving engineering organization.

• 10+ years of experience in chip/IC development as an engineer, engineering manager, or technical program manager, with at least 3 years as a technical program manager.
• Proven track record managing distributed, multi-region engineering teams.
• Strong understanding of the chip development cycle and waterfall program management methodologies.
• Experience establishing scalable processes and driving predictable delivery in high-growth environments.
• Excellent communication and stakeholder management; ability to influence without authority.
• Experience with complex software/hardware integration and managing external dependencies.

Preferred:

• Prior engineering management ownership of end-to-end chip execution (concept to silicon).
• Experience in datacenter chip development and familiarity with modern process technologies and IP/VIP providers.
• Experience scaling engineering orgs at Series B/C startups.
• Familiarity with JIRA, Smartsheet, and project toolchain integrations.

Education Requirements

Not specified.

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.