Principal Technical Program Manager, Hardware/Silicon

Job Title

Principal Technical Program Manager, Hardware/Silicon

Role Summary

Lead program management for end-to-end hardware and silicon projects, establishing processes, milestones, metrics, and cross-team coordination to enable predictable delivery. Partner with engineering, product, and external partners across multiple regions to drive chip development from architecture through tapeout.

Experience Level

Senior — 10+ years in chip/IC development and at least 3 years in a technical program manager role.

Responsibilities

Manage large, distributed hardware programs and improve planning and execution practices.

• Lead end-to-end program management across the chip development cycle (architecture, RTL, verification, emulation, modeling, STA, DFT, physical design, packaging, analog, system design, tapeout).
• Define and enforce predictable milestones for internal teams and third-party IP/VIP/physical design partners.
• Coordinate delivery across teams in North America and India and manage cross-regional dependencies.
• Create metrics, dashboards, and regular reporting to track program health and progress.
• Develop playbooks and best practices for program management and cross-functional delivery.
• Identify, track, and mitigate schedule and quality risks.
• Serve as liaison between hardware teams and company leadership; communicate status and issues clearly.
• Collaborate with Product and partner teams to manage technical and schedule dependencies.

Requirements

Must-have qualifications and skills.

• 10+ years of chip/IC development experience as an engineer, engineering manager, or technical program manager, with 3+ years as a technical program manager.
• Proven experience managing distributed, multi-region engineering teams and external partners.
• Strong stakeholder management and communication skills; ability to influence without authority.
• Deep understanding of the chip development cycle and experience with waterfall program management methodologies.
• Experience establishing scalable processes in fast-moving engineering organizations.
• Experience working at the intersection of software and hardware integration.

Preferred:

• Prior engineering manager experience responsible for end-to-end chip execution (concept to silicon).
• Background in datacenter chip development and familiarity with modern process technologies and IP/VIP providers.
• Experience scaling engineering organizations at Series B/C stage startups.
• Proficiency with JIRA, Smartsheet, and project toolchain integration.
• Experience managing customer-driven timelines and external dependencies.

Education Requirements

Not specified.

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.