Principal System Diagnostics Engineer

Job Title

Principal System Diagnostics Engineer

Role Summary

Principal engineer responsible for designing and delivering low-level diagnostic software, test suites, and automated frameworks to validate network switch hardware, ASICs, and associated platform components. The role partners with hardware, silicon, firmware, and network OS teams and supports board bring-up, failure analysis, and production test readiness.

Experience Level

Senior / Principal level. Typical experience: 10–15 years for candidates with a Bachelor's degree; 5–10 years for candidates with a Master’s degree.

Responsibilities

Primary responsibilities include developing diagnostics, supporting prototype bring-up, and enabling production test integration.

• Design and implement embedded/low-level diagnostic software, test suites, and APIs to exercise and validate switch hardware components.
• Develop test plans for ASICs, high-speed SerDes, memory interfaces (DDR/HBM), PCIe, power management, and thermal control.
• Debug prototype hardware during initial board bring-up and isolate root causes across hardware and software domains.
• Deliver diagnostic coverage for factory manufacturing lines and production-quality test flows.
• Build automated test frameworks and scripts to run diagnostics, collect metrics, and analyze failures.
• Collaborate with Hardware Engineering, ASIC Design, Embedded Firmware, and Network OS teams to define diagnostic requirements and testability hooks.
• Mentor junior engineers on diagnostic software development and hardware debugging techniques.
• Identify hardware-testability and production-readiness risks and drive mitigation and resolution.

Requirements

Key technical requirements and preferred skills. Items marked "Must-have" are required; others are beneficial.

• Must-have: Proficient in C/C++ for embedded or low-level software and scripting with Python or Bash for automation.
• Must-have: Solid experience developing in Linux environments (drivers, kernel concepts, memory mapping).
• Must-have: Practical lab experience with oscilloscopes, logic analyzers, JTAG debuggers to isolate hardware vs. software faults.
• Must-have: Strong analytical, problem-solving, and debugging skills, with a sense of urgency and accountability.
• Must-have: Familiarity with high-speed signal integrity, SerDes, I2C/SPI/MDIO protocols, PCIe, and peripheral management.
• Nice-to-have: Experience with networking ASICs or switch silicon (Broadcom, Marvell, Intel/Barefoot).
• Nice-to-have: Knowledge of networking protocols (Ethernet, TCP/IP, Layer 2/3 switching) and optical transceivers.
• Nice-to-have: Familiarity with U-Boot and ONIE.
• Nice-to-have: Exposure to rack-scale management (OpenBMC, PDU, IPMI, Redfish).
• Nice-to-have: Experience with CI/CD pipelines, automated test infrastructure, and managing test relationships with ODM/JDM/CM partners.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with 10–15 years of related professional experience; or a Master’s degree in a related technical field with 5–10 years of experience. No certifications were specified.

Compensation and Notes

Expected base pay range (USD): 150,680 - 225,700 per annum. This role is eligible for bonus and equity plans.

Additional Information

Reasonable accommodation requests may be directed to Marvell HR Helpdesk at TAOps@marvell.com.

This position may require access to technology subject to U.S. export control laws; non-U.S. applicants may be subject to export license review prior to employment.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.