Principal Static Timing Analysis Engineer

Role Summary

This position involves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems. These SoC devices are multi-core, multi-threaded processor subsystems that support multiple wireless protocols and application functionalities.

Experience Level

Senior; 15+ years in industry.

Responsibilities

The key responsibilities include:

• Develop timing constraints at both the IP and SoC level in collaboration with the designers.
• Improve or evolve existing static timing analysis flows and methodologies.
• Develop required timing signoff criteria, such as aging, on-chip variation, and signal integrity.
• Analyze timing reports using scripting techniques to develop insights and drive rapid timing closure.
• Collaborate with a global design team to resolve complex static timing issues.
• Collaborate with a multi-functional team to drive timing closure for mixed-signal IP integration.

Requirements

Must-have skills include:

• Bachelor or Master’s degree in Electrical or Computer Engineering.
• In-depth knowledge of timing closure flow and methodology.
• Hands-on experience with static timing tools, such as Tempus or Primetime.
• Knowledge of low power design methodology.
• Experience with scripting languages like Perl, Python, Tcl, or shell.
• Knowledge of Verilog and System Verilog.

Education Requirements

Bachelor or Master’s degree in Electrical or Computer Engineering.

About the Company

Company: Silicon Labs

Headquarters: Austin, Texas, USA

Silicon Labs is a leading innovator in low-power wireless connectivity, creating embedded technology that connects devices to improve lives. With a focus on advanced edge connectivity applications, the company provides device makers with cutting-edge solutions and support. Headquartered in Austin, Texas, Silicon Labs operates in over 16 countries, serving markets such as smart home, industrial IoT, and smart cities.