Principal Staff Silicon Design Engineer - DDR Verification

Job Title

Principal Staff Silicon Design Engineer - DDR Verification

Role Summary

Technical lead for DDR interface verification on high-performance server memory products. Lead verification strategy, execution, and sign-off for DDR5, LPDDR5 and DFI interfaces across DIMM implementations.

Work with cross-functional teams (design, firmware, BIOS, software, IP architects, and post-silicon) to ensure system-level memory functionality, performance, and power goals are met.

Experience Level

Senior — principal/staff-level technical lead. Years of experience not specified in the posting.

Responsibilities

Lead verification efforts and own verification delivery for DDR memory interfaces in server products.

• Lead and mentor a team of verification engineers; define and drive verification strategies for DDR5, LPDDR5 and DFI systems.
• Develop and review verification plans, testbenches, coverage models, and emulation strategies; drive verification sign-offs and tape-out readiness.
• Collaborate with IP/domain architects, design, firmware, BIOS and software teams to identify integration risks and deliver architectural solutions.
• Act as product/feature owner for architecture analysis and technical responses to marketing/feature changes.
• Coordinate timing, area/floorplan refinement, pre-silicon bug resolution, and performance/power verification.
• Support post-silicon debug and resolution for functional, performance, and power issues.
• Contribute to verification methodology, knowledge sharing, and cross-team technical leadership.

Requirements

Core technical skills and demonstrated verification delivery for DDR-class memory interfaces.

• Must-have: Expert in SystemVerilog and UVM; strong experience with SystemVerilog assertions, constraints, and coverage.
• Must-have: Proven experience implementing simulation environments and testbenches for DDR5/LPDDR5/DFI and delivering verification sign-offs and tape-outs.
• Must-have: Proficiency in C/C++ and scripting languages such as Python or Perl for testbench and tooling automation.
• Must-have: Experience building VIPs/BFMs for memory interfaces and working knowledge of emulation/FPGA-based validation flows.
• Must-have: GLS, NLP, and XPROP simulation experience (specified as required).
• Must-have: Strong communication, presentation, and collaboration skills; experience leading cross-functional technical work.
• Nice-to-have: Formal verification tool experience beyond standard flows; DFT flow familiarity; prior work on system-level memory architecture across HW/FW/SW.

Education Requirements

Bachelor's or Master's degree in a related discipline preferred.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.