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Principal (STA/Sign-Off) Engineer

Synopsys
June 23, 2026
Full-time
On-site
Sunnyvale, California, United States
Physical Design Jobs, Level - Senior

Job Title

Principal (STA/Sign-Off) Engineer

Role Summary

Lead static timing analysis and sign-off activities for ASIC/SoC implementations. Work with RTL designers, verification, and physical design teams to drive timing closure and deliver sign-off-ready designs.

Experience Level

Senior (Principal). Typically 7+ years of relevant static timing analysis and sign-off experience.

Responsibilities

Primary responsibilities for this role include:

  • Lead STA/sign-off for assigned blocks or full-chip designs and take ownership of timing closure.
  • Develop and maintain timing constraints (SDC) and timing sign-off methodologies.
  • Run and interpret static timing analysis using industry tools (e.g., Synopsys PrimeTime, Cadence Tempus).
  • Debug timing failures, propose fixes with RTL/physical teams, and verify fixes through sign-off flows.
  • Perform multi-corner, multi-mode (MCMM) sign-off and ECO sign-off activities as required.
  • Automate flows and create scripts/tools (Tcl, Python) to improve productivity and repeatability.
  • Prepare timing sign-off reports and documentation for tapeout or release milestones.
  • Mentor and provide technical guidance to less-experienced STA engineers.

Requirements

Key qualifications and skills expected for applicants.

  • Must-have: Extensive experience in static timing analysis and sign-off for ASIC/SoC designs.
  • Must-have: Hands-on experience with STA tools such as Synopsys PrimeTime or Cadence Tempus.
  • Must-have: Strong knowledge of timing constraints (SDC), timing exceptions, and timing methodologies.
  • Must-have: Proficiency with scripting (Tcl, Python) to automate STA flows.
  • Must-have: Practical experience collaborating with RTL, verification, and physical design teams to resolve timing issues.
  • Nice-to-have: Experience with advanced sign-off topics (MCMM, on-chip variation, sign-off under multiple PVT corners).
  • Nice-to-have: Familiarity with physical-design impacts (placement, CTS, ECO flows) and EDA tool flows.

Education Requirements

Not specified.


About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.

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Date Posted: 2026-06-17