Principal STA Engineer

Job Title

Principal STA Engineer

Role Summary

Lead static timing analysis (STA) efforts for high-performance System-on-Chip (SoC) designs to achieve timing closure and sign-off across multiple modes, corners, and voltage domains. Work with implementation, APR and design teams to define constraints, drive ECO strategies, and validate timing for complex interfaces and advanced process nodes.

Experience Level

Senior-level. Recommended: 12+ years of relevant experience; proven track record as an SoC sign-off lead.

Responsibilities

Primary responsibilities include STA setup, timing convergence, and sign-off for complex SoCs.

• Set up and run STA for multi-mode, multi-corner, multi-voltage domain designs; drive timing closure at partition, subsystem and full-chip levels.
• Develop and clean up timing constraints; perform timing analysis, reviews and sign-off.
• Drive convergence by coordinating with APR, implementation and RTL/design teams; provide actionable feedback.
• Define and implement CTS/clock-distribution strategies and advise implementation teams on trade-offs.
• Create and execute ECO strategies, including PrimeTime/Tweaker-based ECO flows.
• Develop automation and STA-tool scripts to improve methodology and throughput.
• Debug implementation issues and propose practical solutions; evaluate timing methodologies and tools across designs and nodes.
• Ensure timing closure of high-speed interfaces (DDR, PCIe, HBM, D2D) and validate affected paths.
• Travel as required (approximately 10%).

Requirements

Must-have technical skills and demonstrated leadership in STA and SoC sign-off.

• Proven experience as SoC sign-off lead on at least two SoCs; ownership of sign-off activities and cross-team coordination.
• Expertise with PrimeTime or equivalent STA tools and timing methodologies.
• Strong understanding of ASIC physical design flow, DFT, and how implementation impacts timing convergence.
• In-depth knowledge of library, memory, and other collateral dependencies affecting STA.
• Experience with variation-aware and aging-aware sign-off, LVF/POCV formats, and ultra-submicron issues (28nm and below).
• Hands-on experience with implementation toolflows (Synopsys/Cadence) and timing ECO execution.
• Ability to develop automation scripts and STA tool methodologies; strong debugging and problem-solving skills.
• Team player with flexibility to work in a dynamic environment.

Education Requirements

Bachelor's or Master's degree in Engineering (e.g., Electrical, Electronic, VLSI) or related technical field is specified in the posting. The role was described with expectation of 12+ years of relevant experience following such a degree.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.