The Principal Software Engineer is responsible for designing and implementing advanced verification environments primarily using UVM. The role involves pre-silicon verification to ensure the functional correctness and performance of system-level solutions.
Mid-level; 5-10 years of experience in verification of IPs, Digital Designs, and SoCs is required.
The primary responsibilities include:
Must-have skills and experience include:
Nice-to-have skills include:
Education requirements are a Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related engineering discipline.
Company: Cadence Design Systems
Headquarters: San Jose, California, USA
Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.
