Principal Software Engineer

Role Summary

We are seeking a Principal Software Engineer to develop performance models and architectural analyses for next-generation DDR memory controller architectures, supporting complex SoC and workload requirements.

Experience Level

Mid-level, with 5+ years of experience in hardware modeling.

Responsibilities

The main responsibilities include:

• Develop cycle-level performance models in SystemC or C++.
• Correlate performance models to match RTL configurations and traffic conditions.
• Collaborate with Memory Architects on feature requirements and architectural specifications.
• Analyze architectural trade-offs across various scenarios.
• Develop synthetic memory traffic that represents real-world applications.
• Automate the generation of performance metrics post RTL simulation.

Requirements

The following skills and qualifications are required:

• BE/B.Tech or ME/M.Tech in ECE, E&TC, CS or related field.
• 5+ years of experience in hardware modeling.
• Strong coding skills in C++, SystemC, and Transaction Level Modeling (TLM).
• Basic understanding of performance principles and queuing theory.

Education Requirements

A degree in Electrical Engineering, Computer Science, or a related field is expected.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.