Principal SOC Physical Verification & Integration Specialist

Job Title

Principal SOC Physical Verification & Integration Specialist

Role Summary

Lead physical verification and top-level integration for EnCharge AI's next-generation SOCs. Own physical assembly from floorplan through tapeout, ensuring manufacturability and power/performance/area (PPA) targets for very large-scale designs.

Serve as the bridge between block implementation, top-level integration, and foundry signoff, collaborating with PD, STA, and foundry partners to resolve physical bottlenecks and complete signoff.

Experience Level

Senior — Principal level. Typically requires 14+ years of hands-on SOC physical design and physical verification experience, with tapeout ownership for large complex SOCs.

Responsibilities

The role owns top-level physical assembly, verification signoff, and integration flow development across multi-hierarchical SOCs.

• Top-level physical integration: lead full-chip floorplanning, bump planning, global power-grid integration, and top-level clock/routing assembly for very large SOCs.
• Define and implement hierarchical physical verification methodologies, boundary conditions, and interface models for partitioned designs.
• Execute and debug full-chip signoff checks (DRC, LVS, ERC, Antenna, ESD, Latch-up) at advanced nodes (5nm/3nm and below).
• Collaborate with Physical Design and STA teams to resolve routing congestion, interface timing violations, and integration fixes without compromising timing closure.
• Work with foundry partners to interpret complex design rules and manage reticle-limit waiver/resolution processes.
• Develop automation, scripts, and utilities to accelerate database merging, PV result parsing, and tapeout cycles.

Requirements

Must-have technical skills and demonstrable tapeout experience; preferred skills listed separately.

Must-have:

• 14+ years of hands-on SOC physical design and physical verification experience with proven tapeout ownership on large, complex SOCs (e.g., datacenter, AI accelerators, HPC).
• Deep knowledge of the RTL-to-GDSII flow and physical integration challenges in flat and hierarchical methodologies.
• Strong understanding of Physical Design and Static Timing Analysis (STA) to assess timing impacts of PV fixes.
• Tool proficiency: top-level integration tools such as Cadence Innovus; physical verification suites such as Siemens Calibre (nmDRC/nLVS/PERC) and Synopsys IC Validator.
• Familiarity with chip/package co-design and bump planning workflows.
• High proficiency in scripting and automation (Tcl, Python, Perl) for EDA flow automation and database manipulation.

Nice-to-have:

• Experience with multi-die integration, 2.5D/3D packaging, or chiplet-based architectures.
• Previous leadership of tapeout operations in start-up or fast-paced advanced technology environments.
• Advanced knowledge of custom layout integration and mixed-signal IP drop-in.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

About the Company

Company: EnCharge AI

EnCharge AI develops advanced AI hardware and software systems for edge-to-cloud computing, focusing on in-memory computing technology to deliver high compute efficiency and density with low power consumption. Founded in 2022, the company targets power-, energy-, and space-constrained applications with integrated hardware architectures and software stacks for scalable, reliable AI deployment.