Principal SoC I/O Performance Architect

Job Title

Principal SoC I/O Performance Architect

Role Summary

Define and optimize I/O performance for next-generation SoCs across pre-silicon modeling and post-silicon validation. Influence architecture and design decisions by producing data-driven analysis, performance models, and reproducible workloads used across architecture, design, verification, emulation, firmware/software, and platform teams.

Experience Level

Senior (Principal) level. The role is a principal/executive-technical position; the posting does not specify years of experience but expects senior/principal-level expertise.

Responsibilities

Primary responsibilities include:

• Define performance objectives, analysis methods, and signoff criteria for SoC I/O subsystems (bandwidth, latency, QoS, ordering, flow control, topology, congestion).
• Build, extend, and apply analytical, event-driven, or transaction-level performance models to evaluate architectural options and answer design questions early.
• Analyze performance data from models, simulation, emulation, firmware/software tests, traces, counters, benchmarks, and silicon debug; correlate pre-silicon predictions against RTL, emulation, and post-silicon results.
• Create reusable workloads, synthetic traffic patterns, trace-replay methods, benchmark flows, and KPI-correlation techniques that scale across teams.
• Partner with architecture, design, DV, emulation, firmware, software, validation, and platform teams; communicate tradeoffs clearly in reviews, readouts, and written recommendations.
• Develop automation and AI-assisted workflows to speed parameter sweeps, data reduction, triage, report generation, and model-based exploration.

Requirements

Core expectations and relevant skills.

• Must-have: Strong systems-thinking ability and demonstrated experience using performance evidence to influence architecture or silicon direction.
• Must-have: Hands-on experience with performance modeling, analysis, or post-silicon validation for complex SoC or I/O subsystems; able to reason from data and produce actionable recommendations.
• Must-have: Practical skills analyzing traces, counters, benchmarks, simulation/emulation outputs, and correlating results across pre- and post-silicon platforms.
• Must-have: Effective cross-team communication and technical leadership: presenting tradeoffs, writing clear recommendations, and collaborating across architecture, design, verification, firmware, and platform teams.
• Nice-to-have: Experience with performance models implemented in C++, Python, or SystemC/TLM and with automation or AI-assisted data workflows.
• Nice-to-have: Familiarity with high-performance I/O, interconnect, memory, and coherency technologies (examples: PCIe, CXL, UCIe, UALink, AXI, CHI, IOMMU/SMMU, Ethernet, InfiniBand, NVLink, DMA engines).
• Nice-to-have: Practical experience with emulation, RTL correlation, and silicon debug tools and methods.

Education Requirements

Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline — or equivalent practical experience.

About the Company

Company: Advanced Micro Devices

Headquarters: Sunnyvale, California, USA

Advanced Micro Devices, or AMD, is a global semiconductor company that designs and manufactures microprocessors, graphics processors, and related technologies for a variety of computing devices. Known for pushing the boundaries of innovation, AMD's mission is to deliver high-performance computing solutions for AI, data centers, gaming, and embedded applications. They foster a collaborative, inclusive culture focused on creativity and problem-solving, aiming to drive progress and excellence in technology.