Principal Silicon Design Engineer

Job Title

Principal Silicon Design Engineer

Role Summary

Lead the architecture, RTL design, integration, and verification of high-speed interface IP for next-generation FPGA devices. Act as the senior technical authority across digital, PHY/analog, verification, FPGA, software, and system teams to deliver robust, high-performance interface solutions.

Experience Level

Senior (Principal). Typical background: 12+ years in ASIC/SoC/FPGA/silicon or digital IC design with substantial experience leading high-speed interface IP development and cross-functional engineering programs.

Responsibilities

Technical leadership and end-to-end ownership of high-speed interface IP from architecture through silicon validation.

• Lead architecture and RTL design of complex high-speed interface IP and subsystems, with primary focus on PCIe and related serial technologies.
• Define PCIe MAC, PCS, link, and subsystem functionality including link initialization, equalization, lane management, and control logic.
• Own RTL implementation, verification strategy, synthesis, timing analysis, and silicon validation activities.
• Integrate digital interfaces with PHY/analog IP; collaborate on calibration, equalization, and system-level performance.
• Drive design work on high-speed equalization and signal-processing (Tx/Rx FFE, DFE, CDR, LMS, PAM4-related techniques).
• Analyze and resolve issues in CDC, lint, synthesis, STA, formal verification, and subsystem integration.
• Collaborate with verification teams on functional, formal, simulation, FPGA, testchip, and silicon validation plans.
• Lead design reviews, mentor engineers, and influence architecture and implementation decisions across teams.
• Improve design methodologies, verification strategies, and IP reuse practices.

Requirements

Must-have technical skills, experience, and constraints for the role.

• Must-have: 12+ years experience in ASIC, SoC, FPGA, silicon, or digital IC design.
• Must-have: 8+ years designing and developing high-speed interface IP or digital subsystems, with hands-on RTL development in Verilog and/or SystemVerilog.
• Must-have: 5+ years working with PCI Express (PHY/PCS, MAC, Link) or equivalent high-speed serial interfaces.
• Must-have: Experience with digital implementation and signoff methodologies (lint, CDC, synthesis, static timing analysis, equivalence checking).
• Must-have: Practical experience with high-speed equalization or signal-processing techniques (PAM4, FFE, DFE, CDR, LMS, etc.).
• Must-have: Proven technical leadership, architecture ownership, and mentorship on complex projects.
• Nice-to-have: Experience with PCIe Gen5/Gen6 or higher, PAM4-based interfaces, MATLAB/Simulink modeling, formal verification (SVA, JasperGold), FPGA prototyping, testchip and post-silicon validation.
• Nice-to-have: Experience integrating digital logic with analog PHY IP (PLL, CDR, DFE, equalization) and ATE workflows.
• Must be eligible for any required U.S. export authorizations.

Education Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field is required. A Master's degree or Ph.D. in those fields is preferred. (Source lists degree fields and preferred advanced degrees.)

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.