Principal Signal Integrity Engineer

Job Title

Principal Signal Integrity Engineer

Role Summary

Technical authority for signal integrity (SI) and power integrity (PI) across d-Matrix high-performance AI compute platforms. Lead end-to-end modeling, simulation, lab correlation and translation of results into manufacturable designs spanning die, package, and system PCB.

Focus areas include high-speed SerDes and memory interfaces, multi-chip modules (MCM) PDN design, and mentoring hardware and layout engineers on SI/PI best practices.

Experience Level

Senior-level — requires 12+ years of experience in SI/PI design for high-performance networking, GPUs, or server platforms.

Responsibilities

Accountable for SI/PI strategy, modeling, validation, and cross-team technical guidance.

• Own end-to-end SI/PI for next-generation AI accelerators and chiplet interconnects.
• Lead MCM and package modeling, including interposer routing, micro-bump parasitic extraction, and die-to-die link budgeting.
• Architect and optimize PDNs to meet Z_target and ensure voltage stability under transient AI workloads.
• Perform comprehensive channel simulations (pre/post-layout) and define jitter, crosstalk, and loss budgets for 112G+ channels.
• Drive lab correlation using VNA, TDR, and high-speed oscilloscopes to validate simulations and close the design loop.
• Translate simulation findings into actionable layout and PCB constraints for advanced stack-ups and high-density routing.
• Provide technical mentorship on SI/PI mitigation techniques and best practices.

Requirements

Must-have technical skills and experience.

• 12+ years of SI/PI engineering experience on high-performance networking, GPU, or server platforms.
• Expert-level proficiency with SI and PI tools (examples: Ansys HFSS, Cadence Sigrity, Keysight ADS, Simbeor; Ansys SIwave, Cadence PowerSI, CST).
• Deep experience with 112G SerDes, high-speed memory architectures, PAM4 signaling, and FEC impact on link margins.
• Hands-on measurement experience with 50 GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes.
• Proven ability to define link budgets and convert simulation results into PCB/layout constraints.

Nice-to-have:

• Knowledge of PCB material science (glass weave effects, copper roughness modeling, skin effect loss).
• Experience with Python or MATLAB for processing simulation datasets and automating analyses.
• Familiarity with Open Compute Project (OCP) hardware specifications.

Education Requirements

MS or PhD in Electrical Engineering or a related field with focus on Electromagnetics or Signal Integrity.

About the Company

Company: d-Matrix

Headquarters: Santa Clara, California, United States

d-Matrix is a Santa Clara–based startup developing highly programmable in-memory computing architectures and accompanying software to accelerate generative AI and other AI workloads, focusing on hardware-software co-design for cloud and edge applications.