Principal / Senior Principal STA Full Chip Expert

Job Title

Principal / Senior Principal STA Full Chip Expert

Role Summary

Full-chip Static Timing Analysis (STA) engineer responsible for running and maintaining the global timing flow for next-generation multi-GHz processor SoCs. The role sits in the Processor/ASIC team and interfaces with physical design, RTL, analog, and DFT teams to ensure timing closure and methodology for high-performance chips.

Experience Level

Senior-level. The posting specifies 12–25 years of relevant industry experience.

Responsibilities

Core responsibilities include leading full-chip timing activities, supporting tape-outs, and improving timing methodology and automation.

• Run, support, and maintain the global timing flow using industry-standard EDA tools for full-chip STA.
• Develop, manage, and integrate IP timing constraints; implement constraint pushdown and ECO flows.
• Work with Digital/RTL/Analog/DFT and P&R teams to bring blocks through the global timing flow and ensure timing closure.
• Participate in timing signoff and tape-out activities for high-performance SoCs.
• Create automation and productivity enhancements using scripting (TCL, Perl).
• Provide technical direction, coaching, and mentoring to engineers across teams.

Requirements

Must-have technical skills, practical experience, and compliance requirements.

• Extensive hands-on experience with STA and industry-standard EDA timing tools (PrimeTime experience preferred).
• Proven experience in IP constraint development, constraint management, pushdown, and ECO flows.
• Deep understanding of timing concepts: setup, hold, clocking, timing corners, constraints, noise, and process variation.
• Strong scripting skills (TCL and Perl) for automation and productivity improvements.
• Experience with tape-outs and working toward timing signoff on high-performance SoCs is highly desired.
• Excellent communication skills, self-driven, detail-oriented, and able to work with minimal supervision.
• Ability to mentor and provide technical leadership across teams.
• May require eligibility for access to export-controlled technology; candidates may be subject to export license review.
• Interview integrity: the employer prohibits the use of AI-assisted tools by candidates during interviews.

Education Requirements

Requires a BSEE or MS and 12–25 years of experience running industry-standard EDA tools for global timing (PrimeTime preferred).

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.