Principal RTL Design Engineer, IO & Memory Systems

Job Title

Principal RTL Design Engineer, IO & Memory Systems

Role Summary

Senior engineering role owning design, integration, and implementation of high-speed IO and memory subsystems for a rack-scale AI platform. The engineer will drive architecture, microarchitecture, RTL development, and IP integration to meet performance, power, and area targets.

This is a hands-on role working across system, verification, physical design, and software teams to deliver reliable, high-performance subsystems at scale.

Experience Level

Senior - typically 7+ years of ASIC design experience.

Responsibilities

The role covers the full product lifecycle from exploration to silicon integration. Key responsibilities include:

• Lead architecture exploration and trade-off analysis for IO and memory subsystems.
• Define microarchitecture and write clear block specifications.
• Deliver synthesizable SystemVerilog RTL meeting functionality, performance, and power targets.
• Run front-end design flow: lint, CDC/RDC, synthesis, timing constraints, and DFT readiness.
• Collaborate with STA and physical design on timing closure, floorplanning, and congestion optimization.
• Work with verification and emulation teams to ensure validation coverage and quality.
• Integrate internal and third-party IP (PCIe, Ethernet, CXL, HBM, die-to-die) and evaluate vendor IP.
• Coordinate cross-functional triage of complex functional and performance issues to root cause and closure.
• Apply and promote engineering best practices: code review, testing, refactoring, and reusable flows.
• Improve design and integration methodology, reuse, and flow scalability.

Requirements

Must-have technical skills and experience:

• Strong background in logic design, microarchitecture, and SystemVerilog RTL design and functional verification.
• Experience optimizing for power, performance, and area (PPA).
• Hands-on experience with two or more on-chip or chip-to-chip protocols (examples: AXI, APB, PCIe, Ethernet, UCIe).
• Experience with memory subsystems such as HBM and CXL.
• Ability to read and distill complex IP and protocol specifications into actionable design requirements.
• Proven communicator with a collaborative, ownership-driven approach to problem solving.

Nice-to-have:

• Experience taking ASIC products from concept to silicon.
• Familiarity with emerging scale-up and scale-out protocols (examples: ESUN, SUE, UAL, Ultra Ethernet).
• Design experience with on-chip interconnects, NoC fabrics, switches, arbiters, QoS, or congestion control.
• Knowledge of machine learning hardware or accelerator architectures.

Education Requirements

MS in Electrical Engineering, Computer Science, or a related field (explicitly stated).

About the Company

Company: SambaNova Systems

Headquarters: Palo Alto, CA, United States

Provider of a full‑stack generative AI platform that integrates custom AI accelerator hardware and software. SambaNova delivers the SambaNova Suite and SN40L chip to enable high-performance, on‑premises and cloud deployments for enterprise and government AI workloads.