Principal Quantum Design Verification Engineer

Job Title

Principal Quantum Design Verification Engineer

Role Summary

As a Principal Quantum Design Verification Engineer on the Quantum 1st Party Hardware SoC team, you will lead development of pre-silicon simulation and post-silicon validation strategies for SoC and IP blocks and coordinate internal teams, contingent staff, and external vendors to deliver production-quality designs.

The role spans SoC architecture, quantum hardware, analog design, and physical design throughout the program lifecycle to enable scalable quantum systems.

Experience Level

Senior-level (Principal). Typical expectation is substantial industry experience; equivalent practical experience is accepted. See Education Requirements for degree-and-experience combinations.

Responsibilities

Primary responsibilities include verification planning, execution, coordination, and maintaining verification infrastructure:

• Own verification environments and tests for IP and SoC; validate designs in simulation with pre- and post-layout RTL and netlists.
• Define and execute pre-silicon simulation plans and post-silicon validation/characterization plans for SoC and IP.
• Coordinate contingent staff and external vendors to meet verification deliverables, specifications, and schedules.
• Set up and manage repositories, simulation flows, databases, and bug-tracking systems; log, track, and close issues; drive milestone reviews and status reporting.
• Create test plans covering digital and analog components, including developing Analog Mixed‑Signal (AMS) simulation models.
• Collaborate with DFT, analog mixed-signal designers, verification engineers, physical design, architects, and other front-end teams.
• Align verification methodologies across teams and drive continuous process improvements for at-scale execution.

Requirements

Must-have skills and conditions, followed by preferred (nice-to-have) items.

• Proven track record owning verification for complex SoC or large IP blocks, including simulation and silicon bring-up coordination.
• Experience creating and managing verification flows, testbenches, stimulus generation, simulation environments, and debugging complex designs.
• Experience with Analog Mixed-Signal verification practices, AMS modeling, and silicon characterization through production release.
• Experience coordinating verification across large programs and managing vendors or contingent staff.
• Ability to pass Microsoft cloud background check and satisfy citizenship/eligibility verification required for access to export-controlled information.
• Ability to leverage modern AI tools to improve modeling, analysis, research, and task automation in an AI‑first environment.

Nice-to-have:

• Hands-on expertise with UVM, OVM, and SystemVerilog.
• Proficiency in MATLAB for modeling and visualization; scripting experience in Python, Ruby, or Perl for automation and data analysis.
• Experience writing tests in C and C++.
• Background verifying complex chips such as CPUs, GPUs, AI accelerators, or networking SoCs.
• 10+ years of design verification experience and 5+ years coordinating verification across large SoC/IP programs.

Education Requirements

One of the following: Doctorate in Physics, Engineering, or a related field + 3+ years industry/R&D experience; or Master’s in Physics, Engineering, or related + 6+ years; or Bachelor’s in Physics, Engineering, or related + 8+ years; or equivalent practical experience.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.