Principal Platform Security Architect

Job Title

Principal Platform Security Architect

Role Summary

Technical owner for platform security across Neurophos's electronic integrated circuit (EIC) and the T100 system. This product security role focuses on root of trust, secure/measured boot, device attestation, signed firmware update, telemetry, and key lifecycle for hyperscale deployments.

Works with digital design, firmware, systems, manufacturing, and external hyperscaler reviewers to design, specify, and validate security subsystems that ship on silicon.

Experience Level

Senior — 10+ years in hardware and firmware security architecture on silicon (experience shipping silicon required).

Responsibilities

Main responsibilities include defining and delivering platform-level security for chip and system deployments.

• Maintain and evolve the platform threat model and corresponding security architecture from fab through field.
• Architect and integrate silicon root-of-trust IP, provisioning, fuse/OTP strategy, and debug authorization.
• Define secure and measured boot chain and firmware resiliency behavior.
• Design device attestation using SPDM with DICE identity.
• Specify signed OTA firmware update mechanisms with anti-rollback protections.
• Define security-relevant telemetry and its exposure to datacenter operators.
• Drive compliance with OCP security profiles and DMTF specifications.
• Own key-management lifecycle and related manufacturing/field processes.
• Serve as technical owner for outsourced root-of-trust engagements and support customer security reviews.
• Partner with digital design, firmware, and systems teams to translate security requirements into implementable specifications.

Requirements

Must-have technical skills and experience to perform the role.

• 10+ years in hardware and firmware security architecture with shipped silicon implementations.
• Hands-on experience integrating RoT IP, provisioning flows, and fuse/OTP planning.
• Design of secure boot chains and firmware resiliency aligned to NIST SP 800-193 class requirements.
• Working knowledge of SPDM, DICE, MCTP, and PLDM.
• Practical understanding of cryptographic primitives, key hierarchies, and secure key storage in silicon.
• Ability to write clear security specifications that digital design and firmware teams can implement against.
• Strong communication skills and experience defending architectural decisions to external reviewers and hyperscalers.

Nice-to-have:

• Familiarity with OCP security profiles and Caliptra.
• Side-channel and fault-injection countermeasure design experience.
• FIPS or Common Criteria certification experience and hyperscaler review experience.
• Background in confidential computing, trusted execution environments, or post-quantum migration planning.
• Experience with manufacturing-side provisioning flows and supply chain security.

Education Requirements

BS, MS, or PhD in Computer Science, Electrical Engineering, or a related technical field.

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.