Principal Physical Verification Engineer

Job Title

Principal Physical Verification Engineer

Role Summary

Lead full-chip physical verification signoff for advanced SoC/ASIC designs with end-to-end ownership from block checks through final tape-out. Collaborate with place-and-route, analog/mixed-signal, timing, power, CAD, and foundry/EDA partners to ensure first-time-right silicon at advanced nodes.

Experience Level

Senior — typically 10–15+ years of hands-on physical verification experience for complex ASIC/SoC designs, including multiple production tape-outs.

Responsibilities

Key responsibilities include ownership of signoff flows, debugging, methodology development, and cross-team coordination.

• Own full-chip and block-level PV signoff (DRC, LVS, ERC, PERC, ANT/ESD) and deliver clean GDS for tape-out.
• Manage PV schedules, track violations, and drive closure to signoff-acceptable levels.
• Develop, maintain, and optimize PV flows and automation (Calibre, ICV, ICV/Calibre integration).
• Define and enhance PERC and reliability rule checks (ESD, EOS, EM, current-density constraints).
• Lead floorplanning and power-grid planning to minimize late-stage PV iterations.
• Debug complex DRC/LVS/PERC failures including FinFET-specific and multi-patterning corner cases.
• Validate and qualify new process nodes, rule decks, and DFM/DFY flows with CAD and foundry teams.
• Mentor engineers on PV best practices, root-cause analysis, and signoff criteria.
• Serve as primary technical interface to foundry and EDA vendors for PV and reliability issues and waivers.

Requirements

Must-have technical skills, tools experience, and professional capabilities.

• Extensive hands-on experience owning DRC/LVS/PERC signoff for advanced nodes (proven production tape-out ownership at 5 nm or sub-7 nm FinFET processes).
• Deep expertise with industry PV tools (Siemens Calibre, Synopsys IC Validator) and Calibre/ICV-based flows.
• Experience integrating Cadence Virtuoso layout into PV flows (Virtuoso to Calibre/ICV).
• Strong scripting skills in Python, Perl, Tcl, or Unix shell for automation and flow development.
• Experience with PERC-based reliability flows for ESD, EOS, LUP and current-density checks and signoff criteria.
• Familiarity with DFM/DFY checks, density/fill strategies, and pattern-matching-driven rule decks.
• Solid understanding of physical design (place & route), timing closure, and power integrity and their interaction with PV.
• Proven leadership, problem-solving, and cross-functional communication skills.
• Willingness to travel up to 10% as required.

Nice-to-have:

• Prior experience with mixed-signal or multi-voltage SoCs and hierarchical PV flows.
• Experience driving methodology improvements with EDA vendors and foundries.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering or a related field.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.