Principal Physical Verification Engineer

Job Title

Principal Physical Verification Engineer

Role Summary

Lead full-chip physical verification signoff for advanced SoC/ASIC designs, owning DRC/LVS/PERC/ERC/ANT/ESD checks from block-level verification through final tape-out. Drive PV methodology, flows, and execution to achieve signoff-quality GDS deliveries.

The role partners with place-and-route, analog/mixed-signal, timing, reliability, CAD, foundry, and EDA vendor teams and mentors other engineers on best practices and root-cause analysis.

Experience Level

Senior — typically 10–15+ years of experience in physical verification for complex ASIC/SoC designs.

Responsibilities

Primary responsibilities include ownership of signoff, tool flows, debugging, and cross-functional coordination to ensure first-time-right silicon.

• Own full-chip and block-level PV signoff (DRC, LVS, ERC, PERC, ANT/ESD) for complex SoCs and tape-outs.
• Manage PV schedules, track and resolve violations, and drive convergence to signoff-acceptable error counts; deliver clean GDS for tape-out.
• Develop, maintain, and optimize PV flows and scripts (e.g., Calibre, ICV) for performance, robustness, and automation.
• Define and enhance reliability and PERC checks (ESD, EOS, EM, current-density, point-to-point resistance) with reliability, I/O, and analog teams.
• Lead floorplanning and power-grid planning to reduce PV iterations and avoid late-stage violations.
• Debug complex DRC/LVS/PERC violations including corner-case connectivity, device recognition, FinFET-specific rules, restrictive spacing, coloring, cut-mask and multi-patterning/EUV constraints.
• Partner with CAD to validate new technology nodes, rule decks, and DFM/FILL flows before adoption.
• Serve as the primary technical interface to foundry and EDA vendors for PV and reliability issues, waivers, and methodology improvements.
• Mentor and guide engineers on PV best practices, root-cause analysis, and signoff criteria.

Requirements

Core technical and practical qualifications required to perform the role.

Must-have:

• 10–15+ years of hands-on physical verification experience for complex ASIC/SoC designs, with multiple production tape-outs as signoff owner.
• Proven ownership of DRC/LVS/PERC signoff for at least one 5 nm (or sub-7 nm) production tape-out in a FinFET process.
• Deep experience with industry PV tools (e.g., Siemens Calibre, Synopsys IC Validator) for DRC, LVS, ERC, PERC and ANT/ESD checks.
• Experience integrating Cadence Virtuoso layout into Calibre/ICV flows for DRC/LVS/PERC.
• Strong scripting skills in Python, Perl, Tcl, or Unix shell for automation and flow development.
• Hands-on experience with PERC-based reliability flows (ESD, EOS, LUP, current-density checks), including setup, customization, and signoff criteria.
• Solid understanding of physical design (place & route, timing closure, power integrity) and its interaction with PV signoff.
• Proven problem-solving, debug, and cross-functional communication skills; ability to lead technical closure.
• Willingness to travel approximately 10% of the time.

Nice-to-have:

• Experience with advanced process nodes (5 nm and below) and associated DFM/DFY, density/fill strategies, and pattern-matching rule decks.
• Experience driving PV signoff in digital-on-top, mixed-signal, or multi-voltage SoCs and hierarchical/IP integration.

Education Requirements

Bachelor's or Master's degree in Electrical/Electronics Engineering or a related technical field was specified.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.