Principal Physical Verification Engineer

Job Title

Principal Physical Verification Engineer

Role Summary

Lead physical verification activities for advanced-node ASICs within Broadcom's ASIC Products Division (APD). The role drives chip-level verification, rule-set development, and issue resolution to achieve first-pass silicon success for high-performance networking and AI/ML products.

Work with P&R, process rule decks, and EDA flows on advanced nodes and multi-die integration to deliver tape-outs on schedule.

Experience Level

Senior - 12+ years of relevant experience.

Responsibilities

Primary responsibilities center on chip-level physical verification, rule management, and tape-out support.

• Execute chip-level physical verification (DRC/LVS/ERC/PERC) and drive issue resolution to closure.
• Develop and maintain DRM/runsets and verification tool flows for advanced process nodes.
• Manage rules for top-level floorplan, I/O and bump planning, and chip integration constraints.
• Investigate and resolve physical design issues related to chip assembly and integration.
• Provide technical direction on verification methodologies and runtime optimizations.
• Lead verification efforts during silicon tape-out and RTO activities.
• Collaborate with physical design (P&R) and cross-functional teams to remove integration bottlenecks.
• Develop best-practice guidelines for verification flows and tooling.

Requirements

Must-have skills and experience required to perform the role; preferred items listed separately.

• Must-have: Hands-on experience running physical verification (DRC, LVS, ERC, PERC) on advanced-node chips.
• Must-have: Experience with EDA verification tools and flows such as ICV, Calibre, and Pegasus; rule-deck coding in those environments.
• Must-have: Proven experience resolving chip-level DRC/LVS/EMIR issues and supporting tape-out activities.
• Must-have: Scripting proficiency (Python, Tcl, or Perl) for flow automation and analysis.
• Must-have: Strong verbal and written communication skills and ability to work on-site in San Jose.
• Nice-to-have: Experience with DFM, density/fill strategies, critical area analysis, and yield enhancement techniques.
• Nice-to-have: Familiarity with advanced nodes (3nm/2nm) and 2.5D/3D chiplet integration practices.

Education Requirements

Minimum: Bachelor’s degree in Electrical Engineering or Electronics Engineering. Additionally, the role expects 12+ years of relevant industry experience.

About the Company

Company: Broadcom

Headquarters: Irvine, California, United States

Broadcom is a global technology leader that designs, develops, and supplies a wide range of semiconductor and infrastructure software solutions. The company is known for its innovations in wireless and broadband communications, enabling a connected world.