Principal Physical Design Methodology Engineer

Job Title

Principal Physical Design Methodology Engineer

Role Summary

Lead development and maintenance of RTL-to-GDSII implementation flows for Interface IP, focusing on synthesis, place-and-route, timing closure, power optimization, and automation for advanced process nodes (5nm, 3nm, and beyond).

Work on a global Interface IP Digital Design Methodology team to deliver production-ready flows and reference automation used by IP design teams and EDA tool teams.

Experience Level

Senior — 10+ years of hands-on ASIC digital implementation experience.

Responsibilities

Own and advance production methodology and automation for high-speed IP cores; mentor teams and act as the technical bridge between IP designers and EDA tool developers.

• Define and maintain complete RTL-to-GDSII flows using Fusion Compiler and related Synopsys toolchains.
• Build, test, and deploy synthesis and place-and-route methodologies for high-speed IP and subsystems at advanced nodes.
• Evaluate and optimize DFT insertion, timing closure, power optimization, and EM/IR analysis workflows.
• Develop automation scripts, reference flows, and practical documentation for design teams.
• Translate real-world design challenges into actionable feedback for EDA tool teams.
• Mentor engineers on implementation best practices, timing strategies, and physical-design tradeoffs.
• Drive continuous process improvements, identify bottlenecks, and measure impact on PPA and schedule.

Requirements

Must-have technical skills and domain experience to perform the role.

• Deep expertise with Fusion Compiler or equivalent synthesis/place-and-route tools (ICC2, Innovus), including MMMC optimization, CTS, and physical synthesis.
• Proven track record developing or supporting high-speed digital IP cores or SoCs (SerDes, memory controllers, or similar).
• Strong understanding of the full ASIC physical design flow: IP deliverables, memory compilers, standard-cell libraries, and PDKs.
• Proficient scripting skills in Tcl and Python for flow automation, analysis, and reporting.
• Ability to debug methodology issues, reproduce failures, and implement durable fixes.
• Excellent written and verbal communication; experience producing practical documentation and training engineers.

Nice-to-have:

• Experience with Synopsys timing and power analysis tools such as PrimeTime, PrimePower, RLTA, or CoreTools.
• Familiarity with high-speed interface protocols (PCIe, DDR, USB, Ethernet, HDMI, MIPI, DisplayPort).

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or Computer Engineering. (The posting specifies 10+ years of ASIC digital implementation experience but that is experience rather than an education credential.)

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.