Principal Physical Design/Implementation Engineer

Job Title

Principal Physical Design/Implementation Engineer

Role Summary

Member of the SubSystem Physical Implementation Center of Excellence within the Custom Compute and Storage (CCS) business unit. Lead architecture and execution of RTL-to-GDSII physical implementation for complex SubSystems, delivering reference floorplans and timing-closed partitions to SoC teams. Position is on-site full-time in Santa Clara or Irvine; relocation provided.

Experience Level

Senior — experienced technical lead. Typical background: 10+ years in physical implementation or equivalent combinations of advanced degrees and experience (see Education Requirements).

Responsibilities

Accountable for developing methodologies, executing complex SubSystem implementations, and mentoring engineering teams.

• Architect and develop next-generation physical design methodologies and automation flows for complex SubSystems.
• Provide hands-on leadership for RTL-to-GDSII flows: synthesis, floorplanning, place & route, clock tree synthesis, and timing closure.
• Perform SubSystem hardening and collaborate with RTL teams to close timing, implement ECOs, and fix design bugs.
• Deliver reference floorplans and fully synthesized, timing-closed SubSystem partitions to SOC teams.
• Work with DFT, verification, CAD, and SOC teams to ensure DFT insertion and timing closure at the SOC level.
• Evaluate and drive adoption of emerging EDA tools and collaborate with foundries and vendors on process node issues.
• Serve as technical advisor across projects, influence design decisions, and contribute to roadmap and methodology evolution.
• Mentor and coach senior and junior engineers to promote best practices and technical growth.

Requirements

Technical must-haves and preferred skills.

• Must-have: Deep experience with SoC implementation: large/complex design synthesis, floorplanning, place & route, clock tree synthesis, and timing closure.
• Must-have: Strong Verilog experience and familiarity with RTL static quality checks.
• Must-have: Proficiency in scripting (Perl, Python) for automation and flow development.
• Must-have: Proven track record of delivering production-quality designs on aggressive schedules; effective communication and teamwork.
• Nice-to-have: Experience with memory generation, PCIe/CXL, Ethernet, security and peripheral interfaces.
• Nice-to-have: Experience with DFT insertion/closing timing at SOC level and working with advanced foundry process nodes (2nm/3nm/5nm).

Education Requirements

Bachelor's degree in Computer Science, Electrical Engineering, or related field with 10–15 years of relevant professional experience; or Master's degree or PhD in Computer Science, Electrical Engineering, or related field with 5–10 years of experience; or equivalent professional experience in lieu of a formal degree.

Expected base pay range (USD): 158,600 - 237,600 per annum.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.