Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Join Microsoft’s Compute Silicon & Manufacturing Engineering (CSME) team within Silicon, Cloud Hardware, and Infrastructure Engineering to lead physical design for cloud compute chips. The role is responsible for end-to-end physical implementation of SoC blocks from synthesis to GDS, ensuring signoff-quality timing, verification, and manufacturability.

The position is an individual contributor role working cross-functionally with CAD, RTL/Architecture, DFT, Power & Performance, and technology partners to deliver production silicon at scale.

Experience Level

Senior (Principal). Years-of-experience guidance varies by degree: roughly 7+ years with a PhD, 10+ years with a Master’s, 12+ years with a Bachelor’s, or equivalent industry experience.

Responsibilities

The core responsibilities focus on technical leadership and hands-on execution of physical design and delivery for complex SOC partitions.

• Lead and execute end-to-end physical design flow from synthesis through place-and-route and GDS generation.
• Deliver all signoff stages including static timing, physical verification, EMIR, formal equivalence, and low-power verification.
• Design and implement clock construction and clock tree synthesis (CTS) strategies for high-speed blocks.
• Optimize SOC blocks for timing, power, and area through methodology exploration and data-driven improvements.
• Coordinate across CAD, RTL/design, DFT, architecture, power/performance, technology teams, and external partners.
• Drive improvements to PD tools, flows, and methodologies and own PD execution and handoff quality.
• Communicate project status and technical trade-offs clearly to stakeholders.

Requirements

Must-have technical skills and constraints; preferred items listed separately.

• Demonstrated experience executing PD flows through synthesis, floorplanning, place-and-route, extraction, timing closure, and physical verification.
• Expertise in clock construction/CTS and clock strategies for high-speed designs.
• Hands-on RTL-to-GDS implementation ownership for medium-to-large SOC blocks.
• Production silicon tape-out experience in advanced foundry nodes and familiarity with signoff criteria.
• Strong problem-solving and data-analysis skills; ability to influence tool/flow decisions with data.
• Effective cross-functional communication and collaboration skills.
• Ability to meet Microsoft security and export-control screening requirements, including background checks and verification of citizenship or protected status.

Nice-to-have:

• Experience with low-power design methodologies and SOC PPA trade-offs.
• 20+ years of physical design experience (documented as preferred by employer).
• Experience partnering with PD flow/CAD and PD methodology teams to resolve tooling and methodology issues.

Education Requirements

Degree options listed by employer: Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field (with ~7+ years technical experience); OR Master’s in those fields (with ~10+ years); OR Bachelor’s in those fields (with ~12+ years); OR equivalent practical experience. Fields referenced include Electrical Engineering, Computer Engineering, Computer Science, or related technical disciplines.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.