Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Early member of the physical design team responsible for taking complex ASIC/SoC blocks from floorplan through signoff. The role focuses on implementation quality (performance, power, area), timing and power closure, and establishing physical design methodologies for the company.

Target base salary: $180,000–$260,000 per year, plus equity, benefits, and 401(k).

Experience Level

Senior-level - requires 10+ years of ASIC/SoC physical design experience with multiple successful tapeouts.

Responsibilities

Own and drive physical implementation and closure for complex blocks and top-level integration, and contribute to tooling, flow, and methodology.

• Own physical implementation from synthesized netlist through signoff for complex blocks and major chip portions.
• Develop and optimize floorplans, placement, clock-tree synthesis, routing, and ECOs to meet timing and congestion goals.
• Design and optimize power delivery networks; support IR-drop and electromigration analysis and closure.
• Perform and drive static timing analysis across multiple modes and corners; resolve setup/hold and signal-integrity issues.
• Drive physical signoff activities including DRC, LVS, antenna, density, connectivity, and related verification.
• Partner with RTL, architecture, DFT, verification, package, SI/PI, and other teams to resolve cross-domain issues and recommend architectural changes when needed.
• Develop and improve physical design flows, scripts, automation, metrics, and methodology; evaluate EDA tools and benchmarks.
• Provide technical leadership, mentorship, and serve as escalation point for difficult implementation problems.
• Participate in design reviews, methodology reviews, and tapeout readiness assessments.

Requirements

Key qualifications and skills. Items under "Must-have" are required; "Nice-to-have" are desirable.

Must-have:

• 10+ years of ASIC/SoC physical design experience with multiple successful tapeouts.
• Expert-level knowledge of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification.
• Strong expertise in static timing analysis (multi-mode, multi-corner) and timing closure techniques.
• Deep understanding of power delivery, IR drop, electromigration, and signal integrity.
• Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools.
• Strong scripting and automation skills (Tcl, Python, Perl, or similar).
• Proven ability to independently own complex block implementations through signoff and debug cross-domain issues.
• Effective communication and technical leadership without formal management authority.

Nice-to-have:

• Experience with advanced process nodes, high-frequency or highly interconnected designs, hierarchical/top-level integration, and multi-die/chiplet packaging.
• Experience developing physical design methodologies and automation in early-stage semiconductor environments.
• Experience with EDA tool evaluation, benchmarking, and optimization.

Education Requirements

Not specified.

About the Company

Company: Delos Data

Headquarters: Palo Alto, CA, United States

Stealth-mode Silicon Valley startup building foundational technology to improve performance, scalability, and resiliency of large-scale AI data center clusters. Backed by venture capital and led by experienced founders, the company develops hardware/software solutions and operates across U.S. and Canadian locations.