Principal Physical Design Engineer

Job Title

Principal Physical Design Engineer

Role Summary

Senior technical leader responsible for end-to-end physical implementation and signoff of complex SoCs across advanced process nodes. The role delivers RTL-to-GDSII implementation, timing and signoff closure, and collaborates with Design, DFT, Verification, CAD and signoff teams.

Accountable for design convergence, quality of results, and leading a geographically distributed physical design team to meet project milestones and PPA targets.

Experience Level

Senior - typically 10+ years of physical design experience with successful tape-outs on advanced technology nodes.

Responsibilities

Principal responsibilities include hands-on implementation, signoff activities, and technical leadership across sites.

• Own RTL-to-GDSII implementation: floorplanning, CTS, placement/routing, ECO implementation, and equivalence checking.
• Drive timing closure: SDC constraints, setup/hold closure, multi-mode multi-corner STA analysis and remediation.
• Perform IR/EM analysis, congestion resolution, and power/performance/area (PPA) optimization.
• Lead signoff activities including DRC/LVS physical verification and final signoff flow coordination.
• Troubleshoot and debug physical flows using Cadence- or Synopsys-based toolchains; improve and automate flows where needed.
• Provide technical leadership for a distributed Physical Design team: planning, prioritization, risk identification, and stakeholder communication.
• Collaborate with Design, DFT, Verification, CAD and project leads to manage dependencies and meet schedule targets.

Requirements

Must-have technical skills and experience for immediate effectiveness in the role.

• 10+ years of hands-on physical design experience with successful tape-outs on advanced nodes.
• Proven RTL-to-GDSII implementation skills (floorplan, CTS, placement/routing, ECO, equivalence checking).
• Strong working knowledge of SDC timing constraints and STA methodologies for timing closure.
• Hands-on experience with industry-standard physical design and signoff tools (Cadence and/or Synopsys flows).
• Experience with IR/EM analysis, congestion mitigation, and physical verification (DRC/LVS) and power analysis.
• Demonstrated ability to lead and mentor engineers and to coordinate cross-functional signoff activities across locations.
• Willingness to travel approximately 10% of the time.
• Nice-to-have: strong track record delivering PPA targets, multi-mode multi-corner signoff leadership, and prior experience scaling distributed teams.

Education Requirements

B.Tech., M.Tech. or higher in Electrical or Electronics Engineering (or equivalent discipline). Equivalent practical experience accepted.

About the Company

Company: Analog Devices

Headquarters: Norwood, Massachusetts, USA

Analog Devices is a leading global semiconductor company that bridges the physical and digital worlds, enabling breakthroughs at the Intelligent Edge. With a focus on innovation, ADI develops solutions that drive advancements in digitized factories, mobility, and digital healthcare. The company employs around 24,000 people globally and reported revenues exceeding $9 billion in FY24, creating technologies that transform lives across various sectors.