Principal Mixed Signal Design Verification Engineer

Job Title

Principal Mixed Signal Design Verification Engineer

Role Summary

Senior verification role in Qorvo's Power Management division focused on top-level design verification for analog and power-management ICs including motor drivers, power-loss protection, point-of-load, and battery management solutions. Responsible for defining and executing verification strategies to meet functional and performance specifications and customer use-cases.

The role is customer-facing and collaborates closely with design, test, and silicon teams to ensure first-pass testability and resolve issues discovered during verification.

Experience Level

Senior level — Principal. Requires approximately 12+ years of experience in AMS design or verification.

Responsibilities

Lead verification efforts and coordinate across teams. Key responsibilities include:

• Serve as customer-facing verification lead for catalog and custom power-management ICs.
• Develop and execute metric-driven verification plans based on IC functional, performance, and test specifications, emphasizing customer use-cases.
• Create constrained-random tests and automated checkers in a UVM environment.
• Build high-performance RNM or Verilog-AMS models to support simulations and co-simulation flows.
• Collaborate with design and test teams to identify and resolve issues found during verification.
• Partner with internal teams to ensure device first-pass testability and support silicon debug.
• Automate verification tasks and continuously improve methodologies to align with industry best practices.

Requirements

Must-have technical skills and experience:

• 12+ years of experience in AMS design or verification of analog and power-management ICs.
• Proficiency with UVM: test cases, coverage models, and global checkers.
• In-depth knowledge of power-management building blocks such as LDOs, amplifiers, bandgaps, DCDC regulators, oscillators, and asynchronous state machines.
• Expertise with mixed-signal simulation and debug: SPICE/Spectre and event-based simulators; co-simulation and silicon debug.
• Experience developing RNM or Verilog-AMS models to support time/level simulation.
• Strong problem-solving, debugging, communication, and collaboration skills.
• Ability to travel domestically or internationally up to 10%.

Nice-to-have:

• Experience with Top-Down Design Methodology.
• Shell or Python scripting proficiency.
• Familiarity with SV-UDN/EENET modeling techniques.
• Experience with both GUI and command-line simulation flows.
• Proficiency with SV Assertions and functional coverage; familiarity with AI integration in verification workflows.

Education Requirements

Advanced degree (Master's or higher) in Electrical Engineering or a related field with a strong focus on mixed-signal circuit design and verification is specified as required/preferred in the posting.

About the Company

Company: Qorvo

Headquarters: Greensboro, NC, US

Qorvo supplies innovative semiconductor solutions that enhance connectivity and power for a variety of applications, including consumer electronics, automotive, and healthcare. With a focus on RF and power solutions, Qorvo combines technology leadership and global manufacturing to address complex challenges in fast-growing industries. Their commitment to excellence and innovation drives them to shape the future of wireless communications.