Principal Layout Designer

Job Title

Principal Layout Designer

Role Summary

Responsible for delivering high-quality physical layout for NAND memory products, focusing on Core/Pitch and Periphery blocks. Works across design, CAD, test and process teams to implement layouts that meet design rules, manufacturability, and tape-out requirements.

Experience Level

Senior - 10+ years of layout experience (Principal level).

Responsibilities

Principal responsibilities include hands-on layout, verification support, and cross-team coordination for memory product tape-outs.

• Implement and deliver high-quality layouts for Core/Pitch and Periphery blocks.
• Use Cadence VXL for periphery block layout tasks.
• Debug and resolve LVS, DRC and layout integration issues.
• Create layouts for critical blocks such as Array, Row decoder and Column decoder.
• Apply core/pitch fundamentals (BL/WL pitch) and evaluate WL/BL driver and pre-driver feasibility.
• Perform chip-level integration and die-size calculations; contribute to floorplanning and signal planning.
• Execute secondary layout work: ECO, LCO and DFM fixes.
• Coordinate with Test Development, Design, CAD and layout teams to meet schedules and quality targets.
• Support tape-out activities and understand mask generation and tape-out procedures.
• Mentor junior layout engineers and lead technical problem resolution.

Requirements

Must-have technical skills and experience first; followed by notable advantages.

• 10+ years of physical layout experience in memory or related technologies.
• Proven proficiency with Cadence VXL on periphery blocks.
• Strong LVS, DRC and layout debug/problem-solving skills.
• Hands-on experience laying out Array, Row decoder and Column decoder blocks.
• Practical understanding of BL and WL pitch and driver/pre-driver implementation.
• Experience with chip-level integration and die-size calculations.
• Familiarity with design rules and delivering quality layouts under process constraints.
• Experience executing ECO, LCO and DFM activities.
• Ability to coordinate across TD, Design, CAD and layout teams and meet schedules.
• Hands-on experience with tape-out processes, mask generation and fab-related flows.
• Experience leveraging automation and AI tools to improve layout productivity.
• Demonstrated ability to mentor junior engineers and lead technical tradeoffs.
• Nice-to-have: multiple tape-out support experience.

Education Requirements

Not specified.

About the Company

Company: Micron Technology

Headquarters: Boise, Idaho, USA

Micron Technology is a global leader in memory and storage solutions, dedicated to transforming how the world uses information. The company offers a diverse portfolio of high-performance DRAM, NAND, and NOR memory products under the Micron and Crucial brands. With a commitment to customer focus and technological innovation, Micron drives advancements in artificial intelligence, 5G, and other data-centric applications, empowering users to learn, communicate, and progress.