Principal IC Package Design Engineer
EthernoviaJob Title
Principal IC Package Design Engineer
Role Summary
Lead the architecture, design, and production release of advanced IC packaging for next-generation Ethernet switches and PHYs. Work across Silicon Design, Systems/PCB, Reliability, and external OSAT vendors to deliver manufacturable, high-performance packages.
Experience Level
Senior / Principal level - requires 10+ years of direct IC package design and architecture experience, with leadership responsibility for cross-functional technical decisions.
Responsibilities
Lead package definition and execution throughout feasibility, design, validation, and production ramp.
- Define package concepts: substrate stack-ups, bump/ball maps, pinouts, and cost/performance trade-offs.
- Execute detailed multi-layer package layouts (FCBGA, FCCSP, SiP, MCM) using industry EDA tools.
- Collaborate with SI/PI and thermal engineers for SerDes (56G/112G+) performance, PDN, and thermal targets.
- Specify substrate design rules, routing optimizations, and DFM/DFA constraints for manufacturability.
- Manage OSAT and substrate supplier engagements during NPI and production ramp; resolve manufacturing and assembly issues.
- Bridge chip-package-board co-design between Silicon IC Design and System/PCB teams.
- Track packaging technology trends and influence long-term hardware roadmap (advanced organics, glass substrates, co-packaged optics).
Requirements
Core technical skills and leadership required to deliver high-volume, high-speed package solutions.
- 10+ years of direct IC package design and architecture experience in high-speed networking, automotive electronics, or HPC.
- Proven delivery of complex Flip-Chip BGA (FCBGA), SiP, and multi-chip module designs.
- Expert with package design EDA tools such as Cadence Allegro Package Designer, SiP Layout, or Synopsys 3DIC Compiler.
- Strong foundations in signal and power integrity (transmission lines, crosstalk, PDN); familiarity with extraction/simulation tools desirable (Ansys HFSS/Q3D, Cadence Clarity).
- Deep knowledge of substrate fabrication, assembly limits, and automotive-grade reliability standards (e.g., AEC-Q100).
- Experience managing vendor technical evaluations, negotiating design rules, and resolving OSAT manufacturing issues.
- Effective communicator and leader able to present technical trade-offs to engineering teams and executives.
- Nice-to-have: experience with SerDes >56G, co-packaged optics, and work on automotive or edge networking ASICs.
Education Requirements
B.S. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
About the Company
Company: Ethernovia
Develops advanced automotive communication semiconductors and systems, focusing on digital SoC design and verification for networking, video, DSP and related IP. Startup-stage employer offering pre-IPO stock options and benefits.
