Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
ArmJob Title
Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
Role Summary
The Principal High-Speed I/O Architect will define and design on-chip high-speed interconnect architectures (coherent and non-coherent) for scalable SoC platforms across mobile, automotive, datacenter, networking, and IoT markets. The role partners with SoC architecture, IP, software/firmware, performance, power and physical design teams to deliver implementation-ready specifications and production-quality silicon.
Experience Level
Senior - typically 10+ years of relevant semiconductor architecture or design experience (the posting references 8+ and 10+ years in different sections).
Responsibilities
Primary responsibilities include architecture definition, roadmap, and cross-functional delivery of high-speed I/O subsystems.
- Architect PCIe, CXL and UA Link subsystems, covering link-level behavior, transaction flows, ordering models, and host/device integration.
- Define coherent and non-coherent communication architectures and roadmaps for high-speed I/O IP and subsystems.
- Lead early customer architecture engagements and produce implementation-ready specifications.
- Collaborate with performance, power, and physical design teams to optimize bandwidth, latency, and system efficiency.
- Integrate Arm IP with high-speed I/O subsystems to meet compute, memory, and interconnect performance targets.
- Partner with software, firmware, and platform teams to optimize end-to-end solutions.
- Perform use-case exploration, workload analysis, and performance modeling to guide architecture decisions.
Requirements
Must-have technical skills and capabilities.
- Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transactions, ordering, and memory expansion/pooling.
- Strong understanding of coherency protocols, hierarchical cache design, and system-level coherency architectures.
- Experience with die-to-die or chiplet connectivity and host/device integration of high-speed I/O.
- Track record collaborating with performance, power, and physical design teams on subsystem implementation and optimization.
- Knowledge of heterogeneous compute, security, caching, and memory system design as it relates to interconnects.
- Demonstrated communication, leadership, and stakeholder-influence skills across multi-functional teams.
Nice-to-have:
- Proven delivery of complex projects on schedule and to specification.
- Ability to adapt in dynamic environments and improve existing designs and processes.
Education Requirements
Bachelor's or Master’s degree in Electrical or Computer Engineering (or equivalent practical experience). The posting explicitly allows equivalent experience in lieu of the listed degrees.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
