Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
ArmJob Title
Principal High-Speed I/O Architect (PCIe, CXL, UA Link)
Role Summary
Design and lead architecture for high-speed on-chip interconnects and I/O subsystems (PCIe, CXL, UA Link) for scalable SoC platforms across markets including mobile, automotive, datacenter, networking, and IoT. Work with cross-functional teams to produce implementation-ready specifications and optimize system-level bandwidth, latency, power, and security.
Experience Level
Senior-level. The posting indicates senior/principal expectations with multi-year experience in semiconductor architecture; source references 8+ years on protocol and coherency topics and 10+ years tied to the listed degree requirement.
Responsibilities
Key responsibilities include system and IP architecture, customer engagements, and cross-team optimisation.
- Architect high-speed interconnect subsystems (PCIe, CXL, UA Link) and define coherent and non-coherent communication architectures for SoCs.
- Define IP and subsystem roadmaps for high-speed I/O and interconnect technologies in partnership with SoC architecture and core technology teams.
- Lead early architecture engagements with customers to capture system requirements and deliver implementation-ready specifications.
- Collaborate with performance, power, and physical design teams to optimize subsystem behavior, bandwidth, latency, and power-efficiency.
- Develop SoC architectures that integrate Arm IP and high-speed I/O subsystems to meet compute, memory, and interconnect targets.
- Partner with software, firmware, and platform teams to optimize end-to-end hardware and system software interactions.
- Support use-case exploration, workload analysis, and performance modeling to guide architectural trade-offs.
Requirements
Must-have technical skills and demonstrated experience.
- Extensive experience with coherency protocols, hierarchical cache design, and system-level coherency architectures (explicitly listed as 8+ years for protocol/coherency work).
- Deep expertise in PCIe, CXL, and UA Link protocols, including link-level behavior, transaction flows, ordering models, memory expansion/pooling, die-to-die or chiplet connectivity, and host/device integration.
- Proven collaboration history with performance, power, and physical design teams on high-speed I/O stacks.
- Strong knowledge of heterogeneous compute, security, caching, and memory systems.
- Demonstrated communication and leadership skills with ability to influence executive stakeholders and cross-functional teams.
Nice-to-have:
- Experience delivering complex projects on schedule and to specification.
- Ability to adapt to dynamic priorities and challenge existing approaches constructively.
Education Requirements
Posting cites a Bachelor’s or Master’s degree (or equivalent practical experience) in Electrical Engineering or Computer Engineering (or related technical field). The listing also associates degree holders with 10+ years of experience; equivalent practical experience is accepted.
About the Company
Company: Arm
Headquarters: Cambridge, United Kingdom
ARM is a global leader in semiconductor and software design, driving innovation in computing technology. The company specializes in designing processors and systems that provide the essential building blocks for electronic devices. ARM's architecture is widely used in smartphones, servers, and IoT devices, and its collaborative culture fosters bold thinking, diversity, and high-impact benefits for its talented workforce.
