Principal High-Speed Analog Mixed Signal Design Engineer

Job Title

Principal High-Speed Analog Mixed Signal Design Engineer

Role Summary

As an Analog IC Design Principal Engineer within Central Engineering, you will deliver high-speed, low-power analog mixed-signal IP used across Marvell's product lines (data center, networking, automotive, storage). The role owns complex analog blocks and contributes to architecting and delivering SerDes and high-speed wireline solutions.

Experience Level

Senior — typically requires 10+ years of relevant industry experience in high-speed analog/mixed-signal IC design.

Responsibilities

Primary responsibilities include technical leadership, full-cycle design, validation, and cross-functional coordination for high-speed analog mixed-signal circuits.

• Own design of complex analog blocks and complete analog macros.
• Design and develop high-speed, low-power analog mixed-signal circuits for SerDes die-to-die communication and high-speed wireline applications.
• Lead designs of TIA, TX drivers, ADCs, DACs, regulators, clock generation and distribution, DLLs, CTLE, VGA, and custom high-speed digital circuits.
• Collaborate with system and architecture teams to select optimal circuit solutions based on cost, performance, and implementation risk.
• Supervise, coach, and provide technical direction to junior engineers; coordinate and guide layout activities to ensure design accuracy and performance.
• Conduct post-silicon testing, lab characterization, debugging, and validation of analog mixed-signal circuits.
• Prepare and maintain detailed design documentation; participate in and lead design reviews to ensure quality and compliance with requirements.
• Work cross-functionally to ensure successful project execution and transfer to production.

Requirements

Must-have technical skills and experience; concise list below.

• 10+ years of industry experience in high-speed and low-power analog/mixed-signal design on advanced CMOS technologies.
• Proven track record of bringing multiple tape-outs to production.
• Ability to assess design trade-offs and select solutions aligned with business needs and implementation risk.
• Experience identifying, analyzing, and resolving complex design challenges to ensure robust circuit performance.
• Experience overseeing layout engineers and ensuring layout meets performance, area, and reliability requirements.
• Proficiency in post-silicon validation with hands-on lab equipment for debugging and characterization.
• In-depth knowledge of CMOS process technology, device physics, and effects of process variation.
• Proficiency with EDA tools for schematic capture, simulation, layout, and verification (e.g., Cadence, Synopsys, Mentor Graphics).
• Good understanding of related domains: RTL, firmware, design verification, design-for-test, and physical design.
• Strong communication and teamwork skills; ability to lead technical discussions and mentor others.
• Nice-to-have: extensive experience specifically in high-speed TIA and/or TX driver design.

Education Requirements

MS or PhD in Electrical Engineering is specified in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.