Principal Hardware Engineer - 3rd Party IP Engineer

Job Title

Principal Hardware Engineer - 3rd Party IP Engineer

Role Summary

Member of the Central Engineering 3rd-party IP management team responsible for bringing subcontracted memory interface IP (DDR/LPDDR/GDDR/HBM/eMMC) under Marvell's IP umbrella and ensuring correct integration into SoC designs.

The role coordinates across sales, design centers, and external IP providers to validate IP developer competence, oversee development, ensure technology and test compliance, and support silicon validation. This role is eligible to participate in Marvell's bonus and equity plans.

Experience Level

Senior. Typical experience guidance: 10–15 years with a Bachelor's degree, or 5–10 years with a Master’s/PhD (see Education Requirements).

Responsibilities

Key responsibilities include:

• Integrate 3rd-party memory interface IP (DDR/LPDDR/GDDR/HBM/eMMC) into SoC designs, addressing PHY integration, timing analysis, packaging, and multi-chip packaging challenges.
• Define core requirements and validate IP developer competence throughout the IP lifecycle.
• Manage 3rd-party IP developers: create statements of work, lead progress reviews, and drive issue resolution using vendor reporting tools.
• Advise Marvell design centers on IP integration and conduct joint reviews with design teams and IP providers.
• Ensure technology compliance, test compliance, and participate in silicon validation and post-silicon activities at customer sites.
• Support sales efforts by assessing vendor IP against customer requirements and helping win bids.
• Lead supplier issue resolution activities (including 8D follow-through for significant issues).

Requirements

Must-have skills and experience:

• Deep understanding of DDR-type interfaces and the challenges of SoC PHY integration, timing analysis, packaging, and multi-chip integrated packaging.
• Proven experience managing 3rd-party developers/vendors and performing project management tasks for external IP delivery.
• Broad exposure to ASIC design flows required for chip release, including logic synthesis, physical design, timing closure, DRC/LVS, formal verification, and electrical checking.
• Solid knowledge of Design-for-Test (DFT) concepts including logic insertion, test generation, scan, and embedded core testing.
• Strong communication and customer-management skills; ability to lead reviews and coordinate cross-functional teams.
• Willingness to perform limited travel for post-silicon validation at customer sites.

Education Requirements

Bachelor’s degree in Computer Science, Electrical Engineering, or a related field with 10–15 years of related professional experience; OR Master’s degree and/or PhD in Computer Science, Electrical Engineering, or a related field with 5–10 years of experience. No certifications or alternative equivalent-experience language is specified elsewhere in the posting.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.