Principal Hardware Design Engineer

Job Title

Principal Hardware Design Engineer

Role Summary

The Principal Hardware Design Engineer will define and drive system-level architecture, signal integrity (SI), and power integrity (PI) strategy for high-speed PAM platforms. This individual contributor role sits in Central Engineering and partners with package, PCB, SI, and system teams to deliver validated SoC hardware platforms.

The position requires leading technical decisions, coordinating simulation-to-lab correlation, and representing design direction with customers and industry forums.

Experience Level

Senior — typically 10–15+ years of relevant experience in high-speed hardware and system architecture.

Responsibilities

Core responsibilities include system architecture, SI/PI strategy, and cross-team technical leadership.

• Define system architecture for 224G and 448G PAM platforms across package, PCB, and interconnect domains.
• Lead end-to-end Signal Integrity and Power Integrity strategy to meet system performance targets.
• Drive system-level modeling methodologies, including IEEE COM and SystemVue-based analysis.
• Establish and standardize correlation flows between simulation and lab measurement across teams.
• Lead complex system-level debugging and root-cause analysis activities.
• Provide technical leadership across hardware, SI, package, and system engineering functions.
• Influence design standards, best practices, and future high-speed technology directions.
• Engage with customers, vendors, and industry forums on advanced high-speed design topics.
• Contribute to design, implementation, and validation of SoC validation platforms and implementation guidelines.

Requirements

Must-have technical skills and experience.

• 10–15+ years experience in high-speed hardware design and system architecture.
• Deep expertise in Signal Integrity, Power Integrity, and channel modeling.
• Hands-on experience with PAM4 systems targeting 224G and beyond.
• Expert-level experience with SystemVue and IEEE COM-based system simulations.
• Experience with 3D EM tools and advanced modeling techniques.
• Strong understanding of IEEE/OIF standards and compliance frameworks.
• Proven ability to lead complex, cross-functional technical initiatives and to coordinate simulation-to-lab correlation.
• Excellent debugging and root-cause analysis skills at system level.
• Strong communication skills for collaboration with internal teams, customers, and vendors.

Education Requirements

Bachelor's or Master's degree in Electrical Engineering or a related technical field.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.