Principal Hardware Architect

Job Title

Principal Hardware Architect

Role Summary

Principal Hardware Architect on the Cloud Silicon & Manufacturing Engineering (CSME) team within Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE). The role defines and delivers next-generation PCIe/CXL I/O architectures and subsystems for Azure SOC platforms, focusing on performance, scalability, reliability, and full-stack optimization across the memory hierarchy.

The architect will work with vendors, performance modeling, strategic planning, and cross-functional teams (design, DV, firmware, system software) to drive architecture from concept through silicon production and deployment.

Experience Level

Senior / Principal level. Typical expectation: experienced architect with long-track record (10+ years preferred) in SoC or I/O architecture and subsystem delivery.

Responsibilities

Key responsibilities include:

• Architect and develop PCIe Gen7 subsystem and related I/O subsystems.
• Evaluate vendor IP and make technical recommendations for integration.
• Collaborate with performance modeling teams to analyze SOC/platform Azure I/O workloads and identify optimization opportunities.
• Work with Strategic Planning, Architecture, and internal customers to capture workload/use-case requirements and enable full-stack optimizations within the memory hierarchy.
• Drive cross-team collaboration to produce scalable, high-performance, production-quality SOC I/O subsystems.
• Lead definition of next-generation PCIe/CXL architecture for Azure silicon platforms.

Requirements

Must-have and preferred qualifications summarized; see Education Requirements for degree/experience combinations.

• Must-have: Ability to pass Microsoft Cloud Background Check and meet export-control eligibility (may require proof of citizenship or lawful permanent residency and valid identification).
• Must-have: Proven experience working with vendors and collaborating across cross-functional teams to deliver hardware subsystems.
• Nice-to-have: Deep expertise in PCIe (Gen4/Gen5/Gen6/Gen7) and CXL architecture and coherency models.
• Nice-to-have: Experience delivering PCIe-based subsystems from architecture to silicon production, including post-silicon validation and debug.
• Nice-to-have: Knowledge of I/O virtualization and system interactions (IOMMU, SR-IOV, ATS), RAS, power management, and security architecture in I/O subsystems.
• Nice-to-have: Experience with performance modeling/analysis for hyperscale workloads and leading architecture across multiple programs.

Education Requirements

Doctorate (PhD) in Electrical Engineering, Computer Engineering, Computer Science, or related field + 3+ years technical engineering experience; OR Master’s degree in those fields + 6+ years; OR Bachelor’s degree in those fields + 8+ years; OR equivalent practical experience. Fields of study referenced: Electrical Engineering, Computer Engineering, Computer Science, or related technical fields.

Compensation (summary): Typical U.S. base pay range: USD 142,800 - 274,800 per year. Different ranges apply for the San Francisco Bay Area and New York City metropolitan area (USD 188,000 - 304,200 per year). Additional benefits and pay information: https://careers.microsoft.com/us/en/us-corporate-pay

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.