Principal FPGA Engineer

Job Title

Principal FPGA Engineer

Role Summary

The Principal FPGA Engineer will architect, implement, and verify complex, high-speed FPGA designs for space-based electronic systems supporting DoD, intelligence, and civil space customers. The role works on multi-function RF, processing, networking, and data storage solutions using modern Xilinx/AMD devices and collaborates with hardware and software teams through integration and lab bring-up.

Experience Level

Senior — experienced engineer expected. Experience guidance: 9+ years with a Bachelor’s degree or 7+ years with a Master’s degree (see Education Requirements for details).

Responsibilities

Key responsibilities include architecture, RTL development, verification, and integration of FPGA-based systems for space applications.

• Architect and deliver complete FPGA designs using Vivado and Vivado IP Integrator for Xilinx devices (Zynq UltraScale+, RFSoC, Versal ACAP).
• Develop RTL (VHDL) for DSP, control, and peripheral interfaces; implement efficient data-path architectures and timing-optimized logic.
• Create and maintain simulation testbenches and verification environments to ensure code coverage and functional correctness (SystemVerilog).
• Define and maintain timing constraints; perform static timing analysis and drive timing closure through implementation.
• Integrate embedded ARM processors, DDR4 memory controllers, and high-speed serial interfaces (Aurora, JESD204B/C, PCIe, 1G/10G/100G Ethernet).
• Perform board bring-up and lab verification, using FPGA debug tools (ILA, Vivado HW Debugger) and lab equipment.
• Participate in design and code reviews; document IP- and top-level designs and contribute to FPGA design methodology.
• Mentor junior engineers and provide technical guidance across multi-discipline teams.

Requirements

Must-have technical skills and experience; preferred items listed separately.

• Deep knowledge of FPGA design methodology: synthesis, place-and-route, timing analysis, power analysis, and timing closure techniques.
• Hands-on experience with Xilinx Vivado Design Suite and Vivado IP Integrator.
• RTL design and coding experience in VHDL; experience writing SystemVerilog testbenches for verification.
• Experience with high-speed interfaces and protocols: DDR4, Aurora, JESD204B/C, PCIe, Ethernet.
• Proven ability to create and maintain comprehensive simulation benches and timing constraints.
• Experience with lab bring-up, debug workflows, and FPGA hardware debug tools (Vivado HW Debugger / ILA).
• Strong collaboration skills with hardware and software engineers during integration and system bring-up.
• Nice-to-have: Versal AI Engines experience, Microsemi/Libero experience, familiarity with Git, ModelSim/Questa/Aldec tools, verification libraries (UVVM/UVM), MATLAB/Simulink, Linux, and C/C++.

Education Requirements

Bachelor’s degree in Computer Engineering, Electrical Engineering, or a related technical field is required. Experience guidance from the posting: 9+ years of related experience with a bachelor’s degree, or 7+ years of related experience with a master’s degree.

About the Company

Company: Trident Systems

Developer of space and defense electronic systems specializing in radiation-mitigated FPGA designs, software-defined radios, on-board processors and storage; mission partner to DoD, the Intelligence Community, and civil space customers.