Principal FPGA Digital Engineer - 3

Job Title

Principal FPGA Digital Engineer - 3

Role Summary

Senior FPGA design engineer for the Electro-Optics group in Launch Vehicles, working in Chandler, AZ. The role focuses on FPGA/SoC design verification, integration with hardware/software/algorithm teams, and ensuring designs meet functional and timing requirements.

Experience Level

Senior-level. Qualification guidance provided by the posting: Bachelor's +5 years, Master's +3 years, PhD +1 year.

Responsibilities

Primary responsibilities include design verification, integration, configuration management, and documentation for FPGA-based image processing and I/O functions.

• Collaborate with FPGA engineers and cross-disciplinary teams (hardware, algorithms, software) to resolve design and integration issues.
• Develop and execute advanced test benches to verify functional correctness and timing closure.
• Generate, verify, and integrate I/O and image-processing HDL modules; perform module-level simulation and system integration.
• Manage FPGA bitstream build configurations for multiple use cases and platforms.
• Perform static timing analysis and manage design constraints (timing, power, I/O) to meet performance targets.
• Prepare and maintain design documentation, simulation results, and verification reports.
• Use hardware bench testing and debugging tools to validate designs on target hardware.
• Maintain technical knowledge of FPGA tools, architectures, and industry best practices.

Requirements

Must-have technical skills, tools experience, and security eligibility; preferred skills listed after must-haves.

• Ability to obtain a U.S. DoD Secret security clearance.
• Strong FPGA/SoC design and complex firmware experience using VHDL (preferred) or Verilog.
• Significant experience with AMD Xilinx FPGAs and SoCs and Vivado IDE for implementation and timing closure.
• Experience managing design constraints and performing static timing analysis.
• Proficiency with MOSA interfaces/buses: Ethernet, PCIe, AXI4, UART, SDLC.
• Competency with simulation tools (Questa/ModelSim) and hardware debugging tools (logic analyzers, oscilloscopes).
• Creating and executing verification plans using simulation, analysis, and hardware bench testing.
• Configuration management of FPGA build/bitstream variants and associated documentation.
• Familiarity with OSVVM or UVM verification methodologies (OSVVM preferred).

Preferred / Nice-to-have

• Active DoD Secret clearance at time of hire.
• Experience with missile, seeker, or other high-reliability electro-optical systems and DoD program standards.
• Experience with AMD Xilinx Versal (Gen1/Gen2) and Vitis Unified IDE.
• DDR memory interface design/integration (DDR3/DDR4/DDR5), fabric controllers (AXI), and high-throughput data movement.
• Embedded C/C++ experience for processor/SoC integration and high-speed PCB design/signal integrity knowledge.

Education Requirements

Required: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related discipline with 5 years of relevant experience; OR Master's degree with 3 years; OR PhD with 1 year. The posting allows equivalent practical experience in lieu of degree. Ability to obtain a U.S. DoD Secret security clearance is required; active clearance is preferred.

About the Company

Company: Northrop Grumman

Headquarters: Falls Church, Virginia, United States

Northrop Grumman is a leading global aerospace and defense technology company that provides innovative solutions in mission systems, electronics, and software. With a legacy of significant advancements in technology, we empower employees to tackle complex challenges and create revolutionary systems that enhance global security. Our diverse teams focus on engineering innovation and product development, delivering solutions that support military and civilian customers worldwide.