Principal FPGA Digital Design Engineer

Job Title

Principal FPGA Digital Design Engineer

Role Summary

Support FPGA designs through all phases: architecture, RTL development, synthesis, timing closure, lab bring-up, and product support within the Countermeasure & Electromagnetic Attack Solutions hardware engineering team in Nashua, NH.

Focus areas include high-speed digital design, FPGA security, and mentoring engineering teams on implementation and verification best practices.

Experience Level

Senior — Principal-level. Typically requires 6+ years of relevant FPGA/ASIC digital design experience.

Responsibilities

Primary responsibilities include ownership of FPGA digital design tasks across development phases:

• Contribute to design architecture and system partitioning for FPGA implementations.
• Develop and maintain RTL (VHDL preferred or Verilog) and associated synthesis flows.
• Perform synthesis, place-and-route, static timing analysis, and timing closure.
• Implement clock domain crossing strategies and integrate high-speed interfaces (SERDES, PCIe, DDR2/3/4, LVDS).
• Create basic testbenches and support digital simulation (Modelsim/Questa).
• Support lab bring-up and hands-on debug using internal logic analyzers (ILA/chipscope/signaltap) and lab equipment.
• Drive FPGA security practices, product support, and lifecycle maintenance of designs.
• Mentor junior engineers and collaborate with cross-functional teams.

Requirements

Must-have technical skills, security, and professional attributes:

• Current Secret security clearance or ability to obtain one.
• Minimum 6 years of relevant FPGA/ASIC digital design experience.
• Proficiency in VHDL (preferred) or Verilog HDL and RTL coding ownership.
• Experience with Xilinx Vivado or Intel/Altera Quartus tool flows.
• Familiarity with internal logic analyzers (ILA/chipscope/signaltap) and digital simulation (Modelsim/Questa).
• Experience with static timing analysis, timing closure, and clock domain crossing techniques.
• Experience integrating high-speed interfaces (SERDES, PCIe, DDR2/3/4, LVDS).
• Knowledge of source control systems (Git, CVS, Clearcase, Subversion) and scripting (Perl, Tcl, Python, shell).
• Strong debugging, problem-solving, lab testing, and communication skills; self-starter and team player.

Nice-to-have:

• DSP fundamentals and FPGA DSP implementation experience.
• Matlab/Simulink, SoC design, low-latency design, UVM/SystemVerilog familiarity.
• Domain knowledge in radar, video/EOIR processing, Ethernet/data communications, stepper motor control, or C/C++.

Education Requirements

Bachelor’s degree required; the posting indicates 6+ years with a bachelor’s degree and fewer years may be acceptable with an advanced degree. Specific fields of study are not specified.

About the Company

Company: BAE Systems

Headquarters: London, United Kingdom

Global defense, aerospace and security company delivering products and services for air, land and naval forces, advanced electronics, cyber and intelligence solutions, and space and mission systems for government and commercial customers.