Principal FPGA/ASIC Verification Engineer (Onsite)

Job Title

Principal FPGA/ASIC Verification Engineer (Onsite)

Role Summary

Lead the design, implementation, and verification of testbenches for high-performance digital ASICs and FPGAs. Work within the Microelectronics Technology / Mission Systems team to develop verification environments, drive verification strategy, and provide technical leadership for verification efforts supporting mission-critical programs.

Experience Level

Senior - principal-level role. Candidates typically have multiple years of hands-on ASIC/FPGA verification experience; see Education Requirements for formal experience guidance.

Responsibilities

Deliver verification architecture, test infrastructure, and technical leadership for RTL verification:

• Architect and implement verification environments using SystemVerilog with OVM/UVM.
• Develop written test plans, testcases, and track code and functional coverage.
• Develop testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Design and run chip-level verification using constrained-random testing and assertions.
• Recommend tools and process improvements to the ASIC/FPGA verification flow.
• Provide technical leadership: break down work, plan verification activities, mentor junior engineers, and report status.
• Contribute to engineering estimates for program pursuits and verification schedules.

Requirements

Must-have technical skills, clearance, and work authority; preferred skills listed separately.

• Active, transferable U.S. government Secret clearance required prior to start; U.S. citizenship required.
• Demonstrated experience developing and simulating RTL using VHDL and/or Verilog in a professional ASIC or FPGA environment (posting specifies multi-year experience).
• Proven ability to design, implement, and execute verification testbenches using VHDL and/or SystemVerilog.
• Experience applying chip-level verification methodologies: constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog).
• Familiarity with revision control systems such as Git or Subversion.
• Ability to work independently and lead or mentor junior engineers.

Nice-to-have:

• ASIC/FPGA lab validation and debug experience and familiarity with DFT, manufacturability, and production test.
• Proficiency with Unix/Linux and scripting or software development (C, C++, Python, Perl, shell).
• Experience with industry-standard simulation and synthesis tools (QuestaSim, Synplify, Quartus, Vivado).
• Strong written and verbal communication skills for multidisciplinary teams.

Education Requirements

Typically requires a Bachelor's degree in a STEM field (Science, Technology, Engineering, Mathematics). An advanced degree in a related field is acceptable and is associated with a reduced experience expectation. The posting specifies typical experience expectations tied to education (for example: 8+ years relevant experience with a Bachelor’s, or 5+ years with an advanced degree). Equivalent practical experience may be considered where appropriate.

About the Company

Company: Raytheon Technologies

Headquarters: Arlington, VA, USA

Raytheon Technologies is an Aerospace and Defense company offering advanced systems and services for commercial, military, and government customers worldwide. Formed in 2020 from the merger of Raytheon Company and United Technologies Corporation, it operates through three major business units: Collins Aerospace Systems, Pratt & Whitney, and Raytheon. The company specializes in delivering cutting-edge solutions across various fields including quantum physics, hypersonics, and cybersecurity.