Principal Formal Design Verification Engineer

Job Title

Principal Formal Design Verification Engineer

Role Summary

Lead formal verification strategy and execution for complex IP, subsystem, and SoC designs on the Compute Silicon & Manufacturing Engineering team supporting Microsoft cloud hardware. Work with architecture, design, verification, and manufacturing teams to define verification strategies, drive closure to signoff, and improve verification productivity and quality.

Hybrid role based in Bangalore with an in-office cadence of three days per week.

Experience Level

Senior - typically 12+ years of relevant technical engineering experience with at least 5+ years of hands-on pre-silicon formal verification experience at the IP, subsystem, or SoC level.

Responsibilities

Key responsibilities include planning and executing formal verification activities, developing reusable verification collateral, and driving verification closure.

• Own or lead formal verification of fabric interconnect architectures, IPs, subsystems, and reusable components from planning through signoff.
• Partner with architecture, design, and verification teams to define formal verification strategies, methodologies, test plans, and signoff criteria.
• Develop and enhance formal verification environments, assertions, abstraction models, checkers, and reusable verification collateral.
• Perform root-cause analysis and closure of complex design and verification issues using formal analysis, simulation, and debug.
• Improve verification productivity through automation, methodology improvements, and AI-assisted solutions.
• Coach and mentor engineers in formal verification methodologies, debug techniques, and best practices.

Requirements

Must-have technical qualifications and screening requirements; preferred skills listed separately.

• Must-have: 12+ years of relevant technical engineering experience.
• Must-have: 5+ years of hands-on pre-silicon formal verification experience at the IP, subsystem, or SoC level.
• Must-have: Proven ability to lead verification from planning through signoff and to deliver closure on complex issues.
• Must-have: Experience developing formal verification environments, assertions, assumptions, checkers, and reusable verification collateral.
• Must-have: Strong root-cause analysis, debug, and convergence skills using formal analysis and simulation.
• Must-have: Ability to meet Microsoft background and export-control screening requirements required for this role.
• Nice-to-have: Deep technical expertise in fabric interconnects, coherency protocols, CHI, AMBA, PCIe, CXL, protocol bridges, virtualization, security, or memory subsystems.
• Nice-to-have: Working knowledge of simulation-based verification methodologies (SystemVerilog, UVM, assertions, coverage-driven verification).
• Nice-to-have: Proficiency with Python or similar scripting for automation; experience applying AI-assisted tools to verification workflows.
• Nice-to-have: Experience driving verification across multiple product cycles and building scalable verification flows.

Education Requirements

Minimum of a Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Computer Engineering, Computer Science, or a related technical field.

About the Company

Company: Microsoft

Headquarters: Redmond, Washington, United States

Microsoft is a global technology company that develops and sells software, services, devices, and solutions. Known for its Windows operating system, Office suite, and Azure cloud platform, Microsoft aims to empower individuals and organizations around the world to achieve more. The company fosters a culture of innovation and inclusion, focusing on delivering trusted experiences to customers and partners globally.