Principal Fabric/Network Architect

Job Title

Principal Fabric/Network Architect

Role Summary

Lead the datacenter scale-out networking architecture for Neurophos's T100 accelerator platform. You'll define the end-to-end data path from host networking through the electronic PCIe bridge, NIC attachment, and DMA into HBM, and own the roadmap for future DPU and fabric designs.

Experience Level

Senior — expects a seasoned architect with substantial production experience; the role requests 10+ years of relevant datacenter networking architecture experience.

Responsibilities

Own and specify the network and transport stack that delivers data to the T100 accelerator at datacenter scale.

• Own end-to-end scale-out data path: host network stack, EIC PCIe bridge, NIC attachment, and DMA into HBM.
• Define transport and offload architecture, including RoCEv2 and Ultra Ethernet Transport (UET).
• Specify peer-to-peer DMA topology and ACS policy across the PCIe hierarchy.
• Define queue and completion semantics exposed to the runtime in partnership with software teams.
• Drive NIC vendor selection and manage technical engagement with networking silicon partners.
• Model and evaluate collective communication performance for distributed inference workloads.
• Develop the architectural case and roadmap for a future Neurophos DPU and scale-up fabric.
• Represent the company in standards bodies and the data center networking community; establish networking architecture practices and mentor engineers.

Requirements

Must-have technical skills and experience; preferred skills listed separately.

• 10+ years in datacenter networking architecture with RDMA transports deployed at scale.
• Deep working knowledge of the Linux host networking stack: kernel networking, VFIO, DPDK or libfabric, and IOMMU/IOVA behavior.
• PCIe fluency: root complex vs endpoint roles, bridges, peer-to-peer transactions, ACS, and Gen5/Gen6 signaling and protocol.
• Familiarity with merchant NIC and switch silicon and experience engaging with vendors.
• Proven ability to write architecture specifications consumable by digital design and software teams.
• Strong communication skills and experience leading cross-functional technical discussions.

Nice-to-have / preferred:

• Experience with DPU or SmartNIC architectures and congestion control design.
• Participation in standards bodies such as the Ultra Ethernet Consortium (UEC).
• Experience bringing novel accelerators into production datacenter networks and working with hyperscaler qualification processes.
• Familiarity with collective communication libraries (NCCL, RCCL) and ML inference workload characteristics.

Education Requirements

BS, MS, or PhD in Computer Science, Electrical Engineering, or a related technical field (as stated in the posting).

About the Company

Company: Neurophos

Headquarters: Sunnyvale, California, United States

Startup developing silicon-photonic AI accelerator chips that use programmable metasurfaces and dense optical cells to perform matrix multiplications at the speed of light, targeting large-scale AI inference with much higher energy efficiency and performance than traditional electronic approaches.